CSE 2312 Final

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23 Terms

1
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Which instruction of ARMv7 will store the result after the operation performed?

Reverse Subtract (RSB)

2
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Which one is the result of converting decimal 256 to uint8_t?

Out of range

3
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What is the range (min–max) of data type intN?

–2^(N–1) to 2^(N–1)–1

4
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Which one is the decimal value by converting binary 0b01101101?

91

5
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For SBC R1, R1, R3 in ARMv7, what’s the operation performed?

R1 = R1 – R3 – (1 – C)

6
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What’s the value of R0 after these instructions?

MOV R0, #11

MOV R1, #7

CMP R0, R1

BGT skip

ADDS R0, R0, R1

skip:

SUB R0, R0, #6

5

7
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What is the primary purpose of the IT instruction in ARMv7?

To set up conditional execution of up to four subsequent instructions

8
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Which one is NOT a convention of the ARMv7 procedure-calling mechanism?

The flags values are stored in the PC

9
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Which instruction is typically used in ARMv7 to return from a subroutine?

BX LR

10
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Which register in ARMv7 is used to store the return address during a subroutine call?

R14 (LR)

11
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What’s the value of R1 after these instructions?

MOV R0, #11

MOV R1, #12

CMP R0, R1

BGT skip

MOV R1, R0

skip:

BX LR

11

12
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Which register stores the floating-point status flags?

FPSCR

13
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The result of a VLDR.F64 operation is loaded into which register?

D0 register

14
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Review the function on the right: how many clock cycles will be executed for MOV R0, #4?

0 clock cycles

15
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What is the normalized form for 13.25 in binary?

1.10101 × 2³

16
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How does paging improve system performance?

By reducing fragmentation and keeping frequently used pages in memory

17
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Which of the following describes temporal locality?

Accessing the same memory location repeatedly

18
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If data is not found in any cache level, where is it accessed from?

System memory

19
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Which description for the VFP coprocessor is incorrect?

VCVT instruction supports S registers, D registers, and R registers

20
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What’s the clock cycle of the Intel Core i9-14900K 4.4 GHz Desktop Processor?

0.2273 nanoseconds

21
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What is the drawback of physical memory?

All of the above

22
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In the 3-stage pipeline, which clock cycle is incorrect for the execution of 3 instructions optimally?

C4 (X3; D3)

23
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For the instruction POP {R5, R7, R3}, what’s the order of execution?

POP R3 → POP R5 → POP R7