embedded quiz 1

Vocabulary practice flashcards covering ARM Assembly, CPSR bits, GDB commands, Raspberry Pi 4 hardware limits, and number systems based on the lecture notes.

Microcontroller vs Processor

A microcontroller integrates a CPU with memory and I/O on one chip for embedded control; a processor (like a CPU alone) typically needs external memory/IO support.

RP4 SoC Cores

4x ARM 64-bit Cortex-A72 cores, plus SDRAM controller and video decode (H.264/H.265).

Instruction Execution Chain

High-level code compiles to assembly, which assembles into machine code (opcodes) that the CPU executes.

Flowchart

A graphical/visual diagram showing program flow; easy to read overall structure but hard to modify, best for smaller jobs or documentation.

Pseudocode

Natural-language description of an algorithm; flexible and easy to modify, can evolve into code comments, but has no overall visual structure.

Bare Metal Programming

Code that runs directly on hardware with no operating system present.

EABI

Embedded Application Binary Interface; a compiler directive commonly used for bare-metal programming.

ELF

Executable and Linkable Format; a compiler directive commonly used for assembly programs run under Linux.

as -g Flag

Compiles assembly with debug symbols included so GDB can step through source and see labels/registers.

GDB Command: r or run

Starts (or resumes) execution of the program in the debugger.

GDB Command: i r

Displays the values of all registers, including the CPSR.

GDB Command: s

Steps through the program one instruction at a time.

GDB Command: b

Sets a breakpoint at the given label (e.g., b _start stops execution at the program's entry point).

Makefile Clean Target

A custom target (commonly 'clean') whose recipe deletes build artifacts (.o files and the executable) to force a fresh rebuild.

Makefile Pattern Matching Wildcard (%)

Represents a pattern match, e.g., %.o : %.s means 'for any .s file, build a matching .o file'.

Makefile ifdef/else/endif

Conditional logic in a makefile; e.g., ifdef DEBUG sets flags like -g only when the DEBUG variable is defined.

File Extension .s

Human-readable ARM assembly source code that you write.

File Extension .o

Object file; machine code produced by the assembler (as), not yet linked, with unresolved references.

Executable File (No Extension)

The final linked executable, produced by the linker (ld) from one or more .o files; this is what you actually run.

RP4 GPIO Current Limit (Single Pin)

$16\,mA$ maximum for a single GPIO pin.

RP4 GPIO Current Limit (Multiple Pins)

Stay under about $3\,mA$ per pin when driving multiple GPIOs; total should stay below ~$51\,mA$.

RP4 GPIO 0-8 Default State

Default high with a pullup resistor (~$50\,k\Omega$).

RP4 GPIO 9+ Default State

Default low with a pulldown resistor (~$50\,k\Omega$).

RP4 I2C GPIO Pullups

GPIO 2 and 3 use $1.8\,k\Omega$ pullups to meet the I2C spec, instead of the usual ~$50\,k\Omega$.

2's Complement Negation

Flip (complement) every bit, then add 1. Example: +2 = 00000010 -> complement 11111101 -> +1 = 11111110 = -2.

2's Complement Range (n bits)

$-2^{n-1}$ to $+2^{n-1} - 1$.

Hex Digit to Binary Conversion

One hex digit equals exactly 4 binary bits; two hex digits equal one byte (8 bits).

ARM General Purpose Registers

R0-R12, 32-bit, visible for general programming use.

R13 (SP)

Stack Pointer; used by compilers to track the stack location.

R14 (LR)

Link Register; stores the return address for subroutine calls or exceptions.

R15 (PC)

Program Counter; points to the next instruction, incremented by 4 or loaded with a branch destination.

XZR

The zero register; always reads as 0x00000000.

CPSR

Current Program Status Register; holds condition flags (N,Z,C,V), interrupt masks, and processor mode bits.

CPSR Bit 31 (N)

Negative flag; set to 1 if the signed result is negative, 0 if positive.

CPSR Bit 30 (Z)

Zero flag; set to 1 if the result is exactly zero, cleared otherwise.

CPSR Bit 29 (C)

Carry flag; set on unsigned overflow for addition, or 'no borrow' for subtraction; also holds the last bit shifted out.

CPSR Bit 28 (V)

oVerflow flag; set when a signed overflow occurs.

CPSR Bit 7 (I)

IRQ mask; when set, IRQ interrupts are disabled.

CPSR Bit 6 (F)

FIQ mask; when set, FIQ interrupts are disabled.

CPSR M Bits (4-0)

Processor execution mode bits (User, FIQ, IRQ, Supervisor, Abort, Monitor, Hyp, System).

Overflow (V) Technical Definition

V=1 if there's a carry into bit 31 but not out of it, OR a carry out of bit 31 but not into it.

S Suffix in ARM Instructions

Added to an instruction (e.g., ADDS, SUBS, MULS) to make it update the N, Z, C, V flags in CPSR; the plain instruction (ADD, SUB, MUL) leaves flags unchanged.

ADD vs ADDS

ADD performs addition without touching CPSR flags; ADDS performs the same addition but also updates N, Z, C, V based on the result.

SUB vs SUBS

SUB performs subtraction without touching flags; SUBS performs subtraction and updates N, Z, C, V.

ARM Load-Store Architecture

ALU instructions operate only on registers, never directly on memory; data must be loaded into a register, operated on, then stored back to memory.

MUL Instruction

MUL Rd, Rn, Op2 computes Rd = Rn * Op2 (result fits in one 32-bit register).

UMULL Instruction

UMULL RdLo, RdHi, Rn, Rm computes an unsigned 64-bit product, split across two 32-bit registers (RdHi:RdLo).

SMULL Instruction

Signed 64-bit multiplication, splitting the product across two registers, similar to UMULL but signed.

MLA Instruction

Multiply-accumulate: Rd = Rm * Rs + Rn.

UDIV Instruction

UDIV Rd, Rn, Op2 computes Rd = Rn / Op2 as unsigned integer division; the remainder is truncated (not stored anywhere automatically).

Assembler Directives (.byte / .hword / .word / .float)

Reserve and initialize memory for a byte, halfword, word, or floating-point value respectively, often used to set up data tables.