Chapter 6_ Arithmetic Logic Unit and Data Path

Arithmetic Logic Unit (ALU)

• basic operations of the computers of earlier times are representing and storing numbers

• is the mathematical brain of a computer

• a digital circuit that provides arithmetic and logic operations.

• the fundamental building block of the central processing unit of a computer.

• Loads data from the input register.

• Stores output in an output register after calculation/manipulation.

Registers,

Control Unit

ALU modern CPU contains (2)

Registers

• A small amount of storage available to the CPU.

• can be accessed very fast.

Control Unit

Tells ALU what operation to perform on the available data.

INTEL 74181

• The first ALU (Arithmetic Logic Unit)

• Implemented as part of the 7400 series TTL (TransistorTransistor Logic) integrated circuits.

• Released by Intel in 1970

Data section (or Data Path),

Control section

CPU can be divided into two sections (2)

Bus

• In early computers, were parallel electrical wires with multiple hardware connections.

• A communication system that transfers data between components inside a computer, or between computers.

Address bus,

Data bus,

Control bus

Types of Bus (3)

Address bus

• Transfers memory addresses from the processor to components.

• A one-way communication.

Data bus

• Carries the data between the processor and other components.

• Bidirectional.

Control bus

• Carries control signals from the processor to other components.

• Unidirectional

Registers

• Very fast computer memory which is used to execute programs and operations efficiently.

• Serve as gates, sending signals to various components to carry out little tasks.

Register signals

Are directed by the control unit, which also operates the registers.

Program Counter (PC),

Instruction Register (IR),

Memory Address Register (MAR),

Memory Data Register (MDR),

General Purpose Register

Registers for In-Out Signal Data Storage (5)

Program Counter (PC)

• A CPU register in the computer processor which has the address of the next instruction to be executed from memory

• As each instruction gets fetched, it increases its stored value by 1.

• It is a digital counter needed for faster execution of tasks as well as for tracking the current execution point.

Instruction Register (IR)

• The part of a CPU’s control unit that holds the instruction currently being executed or decoded.

• Specifically holds the instruction and provides it to the instruction decoder circuit.

Memory Address Register (MAR)

• The CPU register that either stores the memory address from which data will be fetched from the CPU, or the address to which data will be sent and stored.

• It is a temporary storage component in the CPU that temporarily stores the address (location) of the data sent by the memory unit until the instruction for the particular data is executed.

Memory Data Register (MDR)

• The register in a computer’s processor, or central processing unit, CPU, that stores the data being transferred to and from the immediate access storage.

• Also known as Memory Buffer Register (MBR).

Data Path

• A data processing action takes place in the CPU, the data involved in that operation follows a particular path.

• Made up of various functional components, such as multipliers or arithmetic logic units.

• Required to do data processing operations.

One Bus Organization

• is used for multiple purposes.

• A set of the five register are connected with the single bus.

• Memory read/write can be done with MAR and MDR.

• The program counterpoints to the memory location from where the next instruction is to be fetched.

• IR will hold the copy of the current instruction.

• at a time only one operand can be read from the bus.

Two Bus Organization

• were developed to overcome the disadvantage of one bus organization.

• there are two buses.

• The general-purpose register can read/write from both the buses.

• In this case, two operands can be fetched at the same time because of the two buses.

• One bus fetch operand for ALU and another bus fetch for register.

• The situation arises when both buses are busy fetching operands, the output can be stored in a temporary register and when the buses are free, the particular output can be dumped on the buses.

• From in-bus, the general-purpose register can read data and

• to the out bus, the general-purpose registers can write data.

in-bus,

out-bus

versions of two bus organizations (2)

OUT bus1,

OUT bus2,

an IN bus

Three buses in Three Bus Organization

Three Bus Organization

• From the out buses, we can get the operand which can come from the general-purpose register and evaluated in ALU and the output is dropped on In Bus so it can be sent to respective registers.

• This implementation is a bit complex but faster in nature because in parallel two operands can flow into ALU and out of ALU.

• It was developed to overcome the busy waiting problem of two bus organizations.

• In this structure after execution, the output can be dropped on the bus without waiting because of the presence of an extra bus.

Multiple Bus Organizations

• Main Advantages

  • Increase in size of the registers.

  • Reduction in the number of cycles for execution.

  • Increases the speed of execution or we can say faster execution.