VIRTUAL MEMORY

What is virtual memory?

Virtual memory gives each process the illusion of its own huge memory starting at address 0, protected from other processes. It allows processes to use more memory than physically available through paging.

How does the OS manage virtual memory with physical memory?

Since physical memory is smaller, the OS maps virtual pages to physical frames as needed.

Differentiate between Virtual Address Space and Physical Memory in the context of paging.

Virtual Address Space is split into pages, while Physical Memory is split into frames. Each page maps to a frame (or not, if swapped to disk).

How is an address broken down in a paged system (e.g., with a 4 KB page size)?

An address is composed of a Page number (high bits) and an Offset (low bits). The offset always stays the same.

Describe the process of Address Translation from a Virtual Address to a Physical Address.

1. A Virtual Address is composed of a Virtual Page Number (VPN) and an offset.

2. The VPN is used for a Page Table Lookup.

3. The lookup provides a Frame Number (PFN).

4. Concatenate the PFN + offset to get the Physical Address.

What happens if a page is not in memory during address translation?

If a page is not in memory, a page fault occurs, and the OS loads the page from disk.

What is a single-level page table?

A single-level page table is essentially an array where the index is the VPN and the entry contains the PFN, a valid bit, and protection bits. It maps virtual pages to physical frames.

What does a 'Valid Bit = 0' in a page table entry indicate?

A 'Valid Bit = 0' indicates a page fault.

What is the purpose of multi-level page tables?

Multi-level page tables, such as a 2-level example where the VPN is broken into an outer index (Page Directory) and an inner index (Page Table), save memory by not needing page tables for empty regions. This reduces memory overhead.

What is a TLB (Translation Lookaside Buffer)?

The TLB is a small, fast cache that stores recent VPN \to PFN translations to speed up address translation.

Differentiate between a TLB Hit and a TLB Miss.

• TLB Hit: Address translation happens fast, without needing to access the page table.
• TLB Miss: The CPU must walk the page table (which is much slower) to find the translation.

When does a page fault occur?

A page fault occurs when:

• The page table entry is invalid.
• The page is NOT in memory and must be loaded from disk.

What is the impact of disk access during a page fault?

Disk access is extremely slow (milliseconds vs. nanoseconds for memory access), which severely impacts performance.

What steps does the OS take after loading a page into a frame due to a page fault?

After loading the page, the OS:

1. Updates the page table.
2. Sets the valid bit = 1.
3. Restarts the instruction that caused the page fault.

What is the general formula for Effective Access Time (EAT) considering TLB hit/miss rates?

EAT = (TLB \; hit \; rate \times TLB \; hit \; time) + (TLB \; miss \; rate \times page \; table \; access \; time)

How is EAT calculated if memory must be accessed twice for page table + data and page faults are included?

EAT = (1 - page \; fault \; rate) \times memory \; access \; time + (page \; fault \; rate \times page \; fault \; service \; time)
(Where memory \; access \; time includes the necessary page table accesses, e.g., 1 for TLB hit, 2 for TLB miss without page fault)

Why must page fault rates be very low for good performance?

Page faults involve disk access, which is orders of magnitude slower (milliseconds) than memory access (nanoseconds). High page fault rates destroy performance.