C7 Fundamentals of Computer Architecture and Instruction Cycle

Binary Number System

System using 0s and 1s for data representation.

Binary to Decimal Conversion

Process of translating binary numbers to decimal.

OR Gate

Logic gate that outputs true if at least one input is true.

NOT Gate

Logic gate that outputs the inverse of the input.

NAND Gate

Outputs false only if all inputs are true.

NOR Gate

Outputs true only if all inputs are false.

XOR Gate

Outputs true if inputs are different.

XNOR Gate

Outputs true if inputs are the same.

Binary Addition

Combining binary numbers to produce a sum.

Instruction Cycle

Steps of fetching, decoding, and executing instructions.

Instruction Set Architecture (ISA)

Defines CPU instruction representation and processing.

Digital Logic

Rules enabling computers to make decisions using binary.

Control Unit (CU)

Component that directs CPU operations and instruction flow.

Arithmetic Logic Unit (ALU)

Performs arithmetic and logical operations in CPU.

Registers

Small storage locations for quick data access in CPU.

Memory Structures

Organized systems for data storage and retrieval.

Logic Gates

Basic building blocks for digital circuits processing binary.

Boolean Algebra

Mathematical foundation for analyzing digital circuits.

Most Significant Bit (MSB)

Highest value bit in a binary number.

AND Gate

Logic gate that outputs true if all inputs are true.

Binary Multiplication

Multiplying binary numbers to produce a product.

Binary Subtraction

Subtracting binary numbers to find the difference.

RISC Architecture

Reduced Instruction Set Computing for efficiency.

CISC Architecture

Complex Instruction Set Computing for versatility.

Error Detection

Methods to identify errors in data transmission.

Data Representation

Encoding information in binary format for processing.

Noise Immunity

Resistance to errors caused by signal interference.

Redundancy Checks

Techniques to ensure data integrity during transmission.

Instruction

Fundamental unit of work in computing.

Opcode

Binary code specifying operation to perform.

Operands

Data manipulated by the instruction.

PC

Program Counter; points to next instruction.

Fetch

Retrieve instruction from memory.

Decode

Interpret instruction and identify operands.

Execute

Perform operation specified by instruction.

Write

Store result back to memory or registers.

Instruction Set

Complete collection of CPU-understood instructions.

Machine Code

Binary representation of instructions.

Instruction Format

Layout of bits in an instruction.

0-address Instruction

Uses stack for operands and results.

1-address Instruction

Uses accumulator for one operand and result.

2-address Instruction

Overwrites one operand with the result.

3-address Instruction

Specifies addresses for two operands and result.

Fetch-Decode-Execute Cycle

Basic operation cycle of a CPU.

ALU

Arithmetic Logic Unit; performs arithmetic operations.

Instruction Register (IR)

Holds the last fetched instruction.

Memory Address Register (MAR)

Holds address for memory access.

Memory Buffer Register (MBR)

Stores data being transferred to/from memory.

Accumulator (ACC)

Stores intermediate results of operations.

Next Instruction Reference

Indicates where to fetch next instruction.

Source Operand Reference

Indicates data source for instruction.

Destination Operand Reference

Indicates where to store operation result.

I/O Device

Module specified for input/output operations.

Fetch Cycle

CU retrieves instruction from memory.

Store Step

Write processed data back to memory.

Decode Cycle

CU interprets instruction and identifies opcode.

Execute Cycle

ALU performs arithmetic operations specified by instruction.

Program Counter (PC)

Holds address of the next instruction.

Memory Data Register (MDR)

Holds data fetched from or to memory.

Current Instruction Register (CIR)

Stores the instruction currently being executed.

Little Man Computer (LMC)

Simulator mimicking von Neumann architecture.

CISC

Complex Instruction Set Computer with varied instructions.

RISC

Reduced Instruction Set Computer with simplified instructions.

Branch Instructions

Direct program flow based on conditions.

Pipelining

Technique to improve instruction throughput.

General-Purpose Registers

Registers used for arithmetic operations.

Microprogramming

Technique for implementing instruction sets.

HLT Instruction

Halts program execution.

INP Instruction

Inputs data into the program.

OUT Instruction

Outputs data from the program.

Address Bus

Transmits memory addresses from CPU.

Data Bus

Transfers data between CPU and memory.

Control Bus

Carries control signals for CPU operations.

Memory Access

Reading or writing data to memory.