computer science

Fetch stage

the address stored in PC is copied into the MAR - address is sent along the address bus to the main memory - the control unit will send a signal to main memory - content stored in the address will be sent along the data bus to MDR - the data received in MDR gets copied into CIR - PC gets incremented

decode stage

the instruction that is stored in the CIR is analysed

control unit splits instruction into opcode and operand

control unit generates the control signals needed for the execute stage

execute stage

the control unit sends control signals to the relevant parts of the cpu

the instruction is performed by the appropriate component

the result is stored either in the accumulator or back in main memory

control unit

decodes the instruction

sends control signals

controls the FDE cycle

manages data flow

program counter

holds the address of the next instruction to be executed

the address help in the program counter gets sent to the MAR

MAR

holds the address of the memory location where data or an instruction is to be fetched

sends the address to memory down the address bus

MDR

used to temporarily store data that is being read from or written into memory

all data to and from memory must travel down the address bus

CIR

holds the current instruction being executed

contents of MDR is copied into CIR

contains the opcode and operand of instruction

accumulator

results of calculations are stored here

checked for conditional branching

stored fata which has come from the MDR or RAM

address bus

carries memory addresses coming from the MAR

it is one-way

control bus

carries command and control signals to and from every component

bi-directional

data bus

carries data and instructions

bi-directional

pipelining

concurrent processing of multiple instructions

one instruction can be fetched whilst the previous is being decoded and the previous being executed

what happens if there is a branch in the pipeline

the pipeline is flushed

von Neumann

shared memory space for instructions and data

instruction and data use the same buses

simple design and cheap to implement

von neumann bottleneck

where instructions and data are competing for the bus

harvard architecture

two memories for data and instruction

separate buses

more complex and expensive hardware

CISC

large instruction set

instructions may take multiple clock cycles

aims to perform operations in one instruction

fewer lines of assembly code

hardware more complex