Mixed - Finals - identification

PLLs are used to act as a _____________ to stabilize the output of the VCO

frequency controller

____________ generates different frequencies from a single source

frequency

Frequency synthesizer

Give 4 uses of Phased Lock Loops

Frequency Controller
Clock Clean up Circuits
Frequency Synthezier
FM Demodulator

When the comparison is in steady state, and the output frequency and phase are matched to the incoming frequency and phase of the error detector

PLL LOCK

Phase shift is constant if the 2 signals have _______________

similar frequencies

Phase shift is varying if the 2 signals have ________________

different frequencies

Used to compare the phases of the input signal with the reference input. The comparison is an error signal that is proportional to the phase difference of the input signal.

The phase detector

technically a Low Pass Filter (LPF)

The Loop Filter

Used to convert (average) the PFD output thereby giving a _______________________

DC voltage proportional to the phase shift

A repeating signal that switches on and off that is important for pulse width modulation (PWM) and PLL

Pulse Train

it averages the pulse train

loop filter

output frequency changes with change in input signal

VCO

Allows the PLL to generate output frequencies that is multiple of the input frequency

Feedback Divider

A time deviation of a signal transition from its ideal position in time.
measured in unit intervals and measured using eye diagrams.

Jitter

Give application of jitter

SSC Clock
CDR

Main Categories of jitter (2)

random jitter
deterministic jitter

Ever present phenomenon that cannot always be predicted
not bounded and described by a gaussian probability distribution

random jitter

bounded jitter with a non-Gaussian probability density function
repetitious at one or more frequencies

deterministic jitter

another word for deterministic jitter

bounded jitter

tool used to analyze signal/data quality

eye diagram

maximum difference between any two adjacent clock periods

cycle-to-cycle jitter

difference in a clocks period from one cycle to the next

cycle-to-cycle jitter

maximum deviation of any clock period from its mean clock period

period jitter

change in a clocks output transition from, its mean clock period over some number of cycles.

Period Jitter

ensures that the clock does not drift across time

period jitter

difference between observed clock edge time and expected clock edge time for each clock edge present

time interval error jitter

measured by subtracting the actual clock edge from the ideal clock edge

time interval error jitter

deviation in edge location with respect to mean edge location

phase jitter

the skew between a stable input clock and the output clock after the PLL has acquired a clock

Phase jitter