TE2002B Module 1

PLD stands for

Programmable logic device

Advantages of PLDs (2)

Integration of a lot of functionality in just one chip.
Allows design changes.

Types of PLDs (2)

Field Programmable
Factory Logic

Types of factory logic devices (2)

ROM
MPGA

ROM stands for

read

MPGA stands for

mask programmable gate array

Main types of field programmable devices (3)

SPLD
CPLD
FPGA

SPLD stands for

simple programmable logic device

CPLD stands for

complex programmable logic device

FPGA stands for

field programmable gate array

Main types of SPLD's (in chronological order) (4)

PROM
PLA
PAL
GAL

PROM stands for

programmable read only memory

PLA stands for

programmable logic array

PAL stands for

programmable array logic

GAL stands for

generic array logic

What does ROM consist of?

interconnected semiconductor devices that store binary data

Main trait of ROM

memory can always be read, never modified

If there are n inputs and m outputs in a ROM, what is its capacity given by?

(2^n words x m bits of word size) bits

Types of ROM (5)

Mask programmable, PROM, EPROM, EEPROM, flash

EPROM stands for

erasable programmable read

EEPROM stands for

electrically erasable programmable read

How did programmable logic start in the 70s?

with AND and OR gates

History of erasability in ROMs (3)

1. They were once

EPROM's erasing disadvantages (3)

Took 10

EEPROM's erasing advantages (4)

Takes 5 ms
Easy to erase
Can be reprogrammed without removing from the circuit
Can erase parts instead of the entire thing

In programmable logic notation, what does a full dot represent?

hardwired connection

In programmable logic notation, what does an x'ed out empty dot represent?

programmable link

In programmable logic notation, what does a line without a dot represent?

not connected

PROM characteristics (2)

fixed AND matrix
programmable OR matrix

PLA characteristics (2)

programmable AND matrix
programmable OR matrix

PAL characteristics (2)

programmable AND matrix
fixed OR matrix

PLA's tradeoff

more versatile, but slower

PAL's advantages (2)

cheaper
easier to program than PLA

In a PAL, AND terms cannot share 2 or more OR gates, this implies that (2)

one function applies only to one OR gate
function changes are independent to each other

GAL characteristics (4)

eraseable and reprogrammable version of a PAL
reprogrammable with flash technology
contain a macroblock with multiplexors and other programmable blocks

how are GAL devices named?

after their I/O capabilities

a GAL is named 22CEV10, how many input pins does it have?

12

a GAL is named 22CEV10, how many pins that can be programmed as either input or output does it have?

10

a GAL is named 22CEV10, how many total pins does it have?

22

a GAL is named 22CEV10, how many D flip flops does it have?

10

a GAL is named 22CEV10, how many OR gates does it have?

10

what does a macrocell contain? (2)

one D flip flop
one OR gate

what do all flip flops have? (3)

a shared clock
asynchronous reset
synchronous preset

what is a CPLD equivalent to?

multiple PLDs in the same chip

Contents of a CPLD (2)

similar logic block amount to a PAL
PIA

PIA stands for

programmable interconnection array

CPLD's architecture is based on PAL's, but...

it adds macrocells with one flip flop, one OR gate, whose inputs are associated to a fixed AND array

CPLD's architecture is based on PLA's, as...

each AND output in a block can connect to a fixed AND array

How are PAL macrocells conncted

with interconnection wires

How do macrocell interconnection wires scale?

by N², with cost scaling exponentially

How is cost mitigated in macrocell interconnection? What is its drawback? (2)

interconnect is partitioned
macrocells don't have all inputs present

LAB stands for

logic array block

LAB consists of

16 macrocells with local routing

what does PIA serve as?

a routing network between LABs

advantage of CPLDs

allows easy design for combinational circuits, like decoders and state machines

disadvantage of CPLDs

scaling the architecture is inefficient when a design requires many flip flops

what is the solution to CPLD's problems?

FPGA

LUT stands for

look up table

LUT main trait

can be implemented to represent any 4

how is logic implemented in FPGAs?

via look up tables in memory

what can the user program in an FPGA? (2)

functions made by each logical block
connections between logical blocks

what does an FPGA consist of?

an array of identical logical blocks with programmable interconnections

main elements of an FPGA (3)

logical blocks
I/O blocks
programmable interconnections

how are elements arranged in an FPGA? (2)

logic blocks are distributed around the FPGA
the space between logic blocks is for the programmable interconnections

what does a typical FPGA cell contain? (3)

4

The D in D flip flop stands for

data

FPGA logic cell modes (2)

normal
arithmetic

how are modes selected in an FPGA?

programmed into the middle multiplexor of a logic cell

normal mode in FPGA

combines inputs into a 4

arithmetic mode in FPGA

outputs are fed to the full adder

Compare logical resource availability between a CPLD and an FPGA (2)

CPLD: few logical resources
FPGA: more storage and logical resources, good for complex circuits

Compare cost between a CPLD and an FPGA (2)

CPLD: cheaper for simpler circuits
FPGA: more powerful, but more expensive

Compare memory between a CPLD and an FPGA (2)

CPLD: non

Compare startup between a CPLD and an FPGA (2)

CPLD: instant on, starts working immediately
FPGA: has to load config data from an external ROM and configure its structure before starting to work