Computer Science Topic 15 - Hardware and Virtual Machines

Describe what is meant by RISC processors

* Uses simple instructions
* Uses fixed length instructions
* Instructions only require one clock cycle
* Uses many registers
* Makes use of pipelining
* Hardwired CU

Describe what is meant by CISC processors

* Uses many instruction formats
* Uses variable length instructions
* Makes use of different addressing modes
* Uses few registers
* Has a large instruction set
* Requires complex circuits
* Frequently uses cache
* Instructions may require many clock cycles
* Programmable CU

State 9 differences between CISC and RISC

- CISC uses more instruction sets

- CISC uses more addressing modes

- CISC uses multi-cycle instructions while RISC uses single-cycle instructions

- CISC instructions are of a variable length while RISC instructions are of a fixed length

- RISC has a faster execution time for insturctions

- Pipelining with RISC is easer

- CISC has a software emphasis while RISC has a hardware emphasis

- RiSC requires fewer transistors on processor chips

Describe the process of pipelining during the fetch-execute cycle

- Instructions are divided into 5 stages

- ...IF, ID, OF, IE, WB

- Each subtask is completed during one clock cycle

- No two instructions can execute their same stage at the same clock cycle

- The second instruction begins in the second clock cycle, while the first instruction has moved on to its second subtask.

- The third instruction begins in the third clock cycle while the first and second instructions move on to their second and third subtasks, respectively, etc.

Describe how interrupts are handled on RISC pipelines

¬ Discard all instructions in the pipeline except for the last instruction in the WB stage

¬ The interrupt handler routine is then applied to this remaining instruction

- Otherwise, the contents of all five stages are stored in registers, allowing them to be restored to its previous status once the interrupt has been serviced

Describe SISD

- Single Instruction Single Data

- Uses a single processor

- Can only handle a single instruction and only uses one data source at a time

- Each task is processed in sequential order

- Does not allow for parallel processing

Describe SIMD

- Single instruction multiple data

- Uses many processors

- They each execute the same instruction but using different data inputs

Describe MISD

- Multiple Instruction Single Data

- Uses several processors

- Each processor uses different instructions but uses the same data source

Describe MIMD

- Multiple Instruction Multiple Data

- Uses multiple processors that can take their own instructions independently

- Each processor can use data from a separate data source

State 4 characteristics of massively parallel computers

* A large number of processors…
* …working on the same program
* Collaborative processing
* Network infrastructure
* Communicates using a message interface

Describe what is meant by a virtual machine

* The emulation of a computer system…
* …using a host computer system
* Using a guest operating system for emulation

State advantages of using a virtual machine

* Virus’ will only affect the guest OS and not the host OS
* Money is saved due to not having to spend money on extra hardware
* Multiple Virtual machines can run on a single host OS
* Legacy software that were previously incompatible can be run

State disadvantages of using a virtual machine

* Guest OS has poorer performance than the Host OS due to the extra load on the Host OS
* Performance of a virtual machine cannot be adequately measured
* Cannot emulate some hardware
* Virtual machine is affected by the weakness of the Host computer

State equations for De Morgan's Laws

¬ NOT(A AND B) \= NOT A OR NOT B

¬ NOT(A OR B) \= NOT A AND NOT B

State equations for the Associative Laws

¬ A + (B + C) \= (A + B) + C

¬ A.(B.C) \= (A.B).C

State equations for the Distributive Laws

¬ A.(B + C) \= (A.B) + (A.C)
(A + B).(A + C) \= A + B.C

¬ A + (B.C) \= (A + B).(A + C)

State equations for the Idempotent Laws

¬ A.A \= A

¬ A + A \= A

State equations for the Identity Laws

¬ 1.A \= A

¬ 0 + A \= A

State equations for the Null Laws

¬ 0.A \= 0

¬ 1 + A \= 1

State equations for the Inverse Laws

¬ A.Ā \= 0

¬ A + Ā \= 1

State equations for the Absorption Laws

¬ A.(A + B) \= A
A + A.B \= A

¬ A + (A.B) \= A
A + A.B \= A + B

State equations for the Commutative Laws

¬ A + B \= B + A

¬ A.B \= B.A

Describe a Half Adder

- A logic circuit which consists of...

- ...a NOR gate for finding the sum bit

- ....an AND gate for finding the carry bit

Describe a Full Adder

- A logical circuit which is able to carry out binary additions with more than two bits

Describe a flip-flop circuit

* A sequential circuit - The output depends on the input value produced from a previous output

Draw a SR flip-flop circuit

What is an invalid combination of inputs for an SR flip-flop?

* One which produces equal values for Q and Q prime
* This is because Q and Q prime should be complements of each other

Draw a JK flip-flop circuit

State the purpose of a flip-flop

To store a single bit

State the Karnaugh map rules

• The values along the top and the bottom follow Gray code rules.

• Only cells containing a 1 are taken account of.

• Groups can be a row, a column or a rectangle.

• Groups must contain an even number of 1s (2, 4, 6, and so on).

• Groups should be as large as possible.

• Groups may overlap within the above rules.

• Single values can be regarded as a group even if they cannot be combined with other values to form a larger group.

• The final Boolean expression can only consider those values which remain constant within the group (that is, remain a 1 or a 0 throughout the group).