334 3rd

SMPS

Regulating transistor on or off

Power fed to energy store (inductor) when off

DC rectifier fed to chopper (transistor)

Pulse source drives chopper with continuous pulses

Feedback monitors output for changes

If changes, pulse source can alter pulse frequency

SMPS Advantages

Smaller components, more efficient (because transistor isn’t ALWAYS on), lighter (because no heavy transformer)

Voltage Doubler

Increases output voltage by doubling input AC voltage using capacitors and diodes.

Voltage Double CCT 1

2 separate ½ wave rectifiers and reservoir capacitors

Input voltage gives dc output

Input peak value + output

First ½ cycle: D1 conducts. Charges c2 to 10v

Second ½ cycle: D2 conducts. Charges c1 to 10v

Output is across negative C1 and positive C2. VC1 + VC2 = 10+10=20v

Voltage Doubler CCT 2

Output comes after a number of cycles

Increases steadily with each cycle of input

Repeated until peak-peak value of the input is doubled

First ½ cycle - ‘A’ as negative with respect to ‘B’

D1 conducts, charges C1 to 10v

Second ½ cycle - ‘B’ is negative with respect to ‘A’

D2 conducts, C1 is shared with C2. Charges C2 to 10v

After number of cycles C2 charge equals own voltage + C2 voltage

Regulator Circuits

TR1 - variable resistance in parallel with RL (LOAD) 

RL and R2 - form potential divider with output taken across RL (LOAD)

D1 (Zener Diode) - provides constant 5.6v at TR1 base.

TR1 emitter - consistent 5v output. 0.6v lower than TR1 base voltage

Regulator Circuits Reduced Load Current

RL (LOAD) increases, R2 current and PD also reduces

Output increases 

Voltage reduction across R2 = Increased forward bias on TR1 = TR1 conducts ‘HARDER’ maintaining constant current & voltage across R2, therefore also RL (LOAD)

Regulator Circuits Voltage Increase

Vr1 feedback turns TR1 on

Collector voltage falls

TR1 conduction drops

Increase output voltage

Series Regulator Circuit

TR1 base voltage held at 5.6v, emitter 0.6v lower = O/P voltage 5v

Reduced load current = 

Voltage reduction across RL = Increased forward bias on TR1 = TR1 conducts ‘HARDER’ = increased load current = output maintained and steady

Shunt Regulator. D1 = 5.3v, Output = ?

Vout = zener voltage + Vbe

        = 5.3v + ~0.7~ 

        = ~6v~

Shunt Regulator. R3 Reduced

Load current (RL) increase

Transistor conducts less due to Vbe reduction = reduced current in R2 =  equilibrium of circuit regained

Shunt Regulator. R3 Short Circuited

Emitter voltage to 0v

R2 limits short circuit current

Protects circuit and transistor

Common Emitter Amplifiers

C1 = Input coupling capacitor = prevent DC from affecting DC bias set by R2 & R4

PD = provide transistor forward bias, ensure TR1 ‘ALWAYS’ on. ~9:1~ between R2 & R4 240:33

R3 = Emitter bias = Raises emitter V = raises base V = TR1 to be biased in linear portion of Vbe/Ic characteristics. Ensures generation of linear undistorted signal voltage

R1= Collector Load Resistor = Provides output V proportional to its’ output current 

C2 = Output signal coupling capacitor = Prevent DC from collector affecting next stage of circuit

Power Amplifier

Class B amplifier

2 or more transistors

Biased transistors = only conducts ½ of input waveform each

1 transistor decrease = other increases

Reduces output voltage & current to 0 = both output waveform halves swing from 0 - 2x the quiescent current = reduces dissipation =  doubles efficiency by ~70%~

Power Amplifier with no signal present

Transistors carry normal quiescent current

Value determined by base bias which is at cut off point (TR ON/OFF)

No input signal = quiescent collector/emitter current 0

Power Amplifier TR1 and TR2

TR1 = amplifies positive ½. TR2 amplifies negative ½ 

As transistor take ~0.7v~ to switch on, amplifiers suffer from crossover distortion 

Transistors not pre-biased to ON = inaccurate replacement of output that has fallen below 0.7v

TRIAC and DIAC Power Controls D1/D2

D1 Allows ONE directional current flow until its met specific value. Then it allows flow

D2 Similar to silicon rectifier

Allows both directional current flow IF there’s current through the gate

TRIAC and DIAC Power Controls R1 HIGH OUTPUT

C2 slowly charges = ‘Slow’ current feed to TRIAC = Limits sine wave reaching load = Load seen as off

TRIAC and DIAC Power Controls R1 LOW OUTPUT

C2 quickly charges = ‘Higher’ current feed to TRIAC = Allows full sine wave at load = Load seen as on

TRIAC and DIAC Power Controls L1/C1

Forms filter that moves unwanted components (rf) of waveform

RF parts are generated in high speed switching, causes interference

TRIAC and DIAC Power Controls R2/R3

Fail safe

Reduce possibility of false triggering of TRIAC 

False triggering of DIAC = fast voltage rises occur on supply lines

TRIAC and DIAC Power Controls C2

C2 slowly charges = ‘Slow’ current feed to TRIAC = Limits sine wave reaching load = Load seen as off

TRIAC/DIAC Power Controls

DIAC - ONE directional flow

TRIAC - BOTH directional if there’s enough current

C2 = Adjustable stable output

L1 & C1 = Filter

R2 & R3 = Fail safe

Circuits with Operational Amplifiers and Integrated Circuits

Op-amp integrator

Feedback occurs via capacitor

Op-amp has same input value whether on or off = voltage across R is Vi and voltage across C is Vo

Bridge Rectifier

smoothing of AC to DC

Effect on waveform when when output load current changes

ratio changes

Slew Rate

rate of change of output voltage

offset

differences in voltage/current between 2 inputs

Drift

offset voltage/current changes from temp changes

propagation delay

time taken between the input reaching a stable condition, to when the output reaches a stable condition

low level output current (IoL)

load current following from gate when output is set to 0

grey encoder used for…

detect angle on a shaft in rotation

methods for preventing damage to components caused by static discharge

wrist strap - ESD wrist strap

ESD shoes, ESD, ESD tools etc

VoH

min output voltage recognised as high by driver

Graded index multimode pro and con

pro - less expensive

con - greater output distortion

VoC

max output voltage recognised as low

ViH

min input V recognised as high by receiver

ViL

max input V recognised as low

NMH - Noise Margin High Formula

VoC - Vih

Fan Out

Number of gates an output can drive from logic gate without falling below its’ specs

Input Bias Current

Average of the 2 currents into the 2 input terminals with output at 0v.

Causes V drop across equivalent source impedance.

Input Offset Voltage

Ideal op amp, both inputs are 0, then output is 0

Real life - imbalances can cause small output voltage.

Can apply small offset V to other input to nullify this

Noise Margin

Tolerance of a digital circuit to V fluctuation (NOISE) on its input/output before it misinterprets a logic level. Ensures reliable IC operation.

Can be split into 2 parameters = NMH (HIGH) and NML (LOW)

Input Offset Current

Difference between 2 input currents when output is 0v

CMRR (Common Mode Rejection Ratio): 

Ideal op-amp, both inputs equal if output is 0v.

Signal applied to both inputs, CMS (Common Mode Signal)  = unwanted noise

Ability of op-amp to suppress CMS = CMRR

HC

High Speed CMOS 

Lower dissipation of power

Lower switching noise

LS

Low Power Schottky

Low noise

Low power dissipation

~7ns propagation delay

ALS

Advanced Low Power Schottky

~4ns propagation delay 

1mW Power 

Most commonly used the series

NML

Amount of noise voltage a circuit can handle at high level before it’s unrecognised as high

NMH:

Max noise voltage tolerable at low logic level before it’s misread as high

Op Amp Switch

resets IC’s output to 0 then restart. 

Circuit mathematical equations

Converts square waves to triangular waves 

Used as integrating part of PID controller

Op amp inputs

Inverting - V1

Non Inverting + V2

Op-amp

Basic differential voltage amplifier. Amplifies difference between input voltages (V1 and V2)

Op amp Variations

V2 > V1 = Positive Vo (output)

V2 < V1 = Negative Vo (output)

V2 = V1 = 0 Vo (output)

Op amp Properties/Characteristics                   

High/Infinite Open Loop Voltage Gain

High/Infinite Input Impedance

Low/Zero Output Impedance

0 Drift

Virtual Earth X        

Ideal Op-Amp

Each Input Draws 0 Current From Signal Source (Infinitely High Input)

Both Inputs At The Same Potential If Op-Amp isn’t Saturated (V1 = V2)

V2 = 0v, means V1 = 0v

Wein Bridge Oscillator

Generates Sine Waves In Large Range of Frequencies

Has Resistors and Capacitors

Wein Bridge Oscillator CONDITIONS

R1=R2=R and C1=C2=C

F = 1/2ℼ x RC.

Minimum Feedback Gain = 3

Phaseshift between input and output = ~0 or 360°~

Monostable Pulse Circuit

Single Pulse

Needs Reset

Time Between

Extend Pulse by Altering C and R values

Asynchronous Mod - 10 Counter

Counts from 0-9 in Binary (0000 to 1001)

Immediately resets back to 0000 on 10th clock pulse

Requires 4 flip flops (JK) because 4 bits are required to count to 10

Asynchronous Mod - 10 Counter - Clock signal

Ripples through alongside combinational logic gate that detects ‘10’, which forces rest

Asynchronous Mod - 10 Counter - External Clock

connected to first flip flop only.

Every other flip flop receives trigger from previous flip flop output = creates ripple effect

Asynchronous Mod - 10 Counter - Counting Sequence

On every clock edge, circuit counts normally up to 9 (1001)

Asynchronous Mod - 10 Counter - 10th State

10th clock pulse arrives = binary count = 1010 (decimal 10). 

In this binary state, the 2nd & 4th bit (Qb & Qd) are both logic high

Asynchronous Mod - 10 Counter - Reset Mechanism

To force counter back to 0 before it continues onto 11 Qb & Qd outputs are fed into NAND gate. 

Both inputs high on a NAND gate = output drops to 0

Asynchronous Mod - 10 Counter - Clearing the counter

The 0 output is wired directly into CLR (clear) pins of all 4 flip flops. Pins are active - low = sudden drop back to 0 = forces flip flops Q outputs back to 0

Starts all over again