CPU and Memory Design, Enhancement, and Implementation

A set of vocabulary flashcards covering important concepts related to CPU and memory design as discussed in the lecture.

Fetch-Execute Cycle

The process where a computer retrieves an instruction from memory and executes it.

Clock Speed

Measured in GHz (gigahertz), it indicates the number of cycles a CPU can perform in one second.

Pipelining

An assembly-line technique in CPUs allowing overlapping execution of instructions.

Superscalar Processing

The ability of a CPU to process more than one instruction per clock cycle.

Cache Memory

A small, fast memory located close to the CPU that stores frequently accessed data.

Hit Ratio

The ratio of cache hits to total memory requests, indicating cache efficiency.

Memory Interleaving

A technique that partitions memory into sections to improve access speed.

Branch Prediction

The method used to guess which way a branch (decision point) in the code will go to improve performance.

Scalar Processing

A processing technique where each instruction is executed one at a time.

Multiple Execution Units

Design in CPUs allowing simultaneous execution of multiple instructions.

Master-Slave Multiprocessing

A system configuration where a master CPU manages tasks assigned to one or more slave CPUs.

Symmetrical Multiprocessing

A system where each CPU has equal access to resources and can determine its own tasks.

Instruction Pointer (IP) Register

A register that holds the address of the next instruction to be executed.

Data Word Width

The number of bits processed by a computer's CPU in a single instruction cycle.

Bus Interface Unit

Component responsible for communicating with memory and I/O devices in a CPU.

Out-of-Order Processing

A method of executing instructions in an order that improves execution speed by avoiding delays.