Lecture Notes on CPU Exceptions and Interrupts

Flashcards reviewing key concepts related to CPU exceptions, privilege levels, and interrupt handling.

What is the purpose of an exception?

To model unexpected events during program execution.

What are the two main types of exceptions?

Synchronous and Asynchronous.

What causes a synchronous exception?

An instruction in the running program (e.g., arithmetic exceptions, invalid memory addresses).

What causes an asynchronous exception?

An I/O device requesting the processor (also known as a hardware interrupt).

Why do computers limit resource access to different processes?

To prevent buggy code from corrupting systems and to ensure security.

What is the purpose of a Supervisor Instruction (SVC)?

It provides a way for user code to request a service from the OS.

What does the CPU do upon receiving a Supervisor Instruction?

The CPU reads arguments from specific registers and executes the requested service.

What is the purpose of an exception vector table?

To determine where to jump to the exception handler when an exception/interrupt is raised.

Where is the exception vector table typically located?

In low memory.

List the steps in Exception Handling

1. Store the cpsr into banked spsr. 2. Set execution mode and privilege level based on exception type. 3. Disable interrupts using the interrupt mask bits in cpsr. 4. Store the return address into banked lr 5. Pushes other registers onto stack 6. Branch to the exception function based on the address from the vector table 7. Execute exception handler 8. Copy lr → pc (movs pc, lr), banked spsr → cpsr 9. Pop the registers back off the stack

Name some ARM Execution Modes

User, IRQ, Supervisor, System

What is the Current Program Status Register (CPSR)?

An ARM register that records the state of the program.

What is a BusFault?

A memory access error in the bus interface.

What are the different registers in the System Control Unit related to fault handling?

SCR (Sleep modes), CCR (stack alignment and memory access behavior), CFSR (details of current HardFault), BFAR (bus address that caused error).

What registers are contained in the BusFault Status Register (BFSR)?

STKERR/UNSTKERR: Stack error, PRECISERR: Error Mem address is in BFAR, IBUSERR: Error reading instruction, BFARVALID: Records if this is a BusFault

What is Fast Interrupt Execution mode (FIQ)?

A fast, low-latency interrupt handling mechanism in high-end ARM that uses banked registers for faster interrupt handling.

Provide an example of a synchronous and asynchronous exception.

Synchronous: Arithmetic overflow. Asynchronous: Hardware interrupt from a peripheral device.

Why does an exception handler require escalated privileges?

To access system resources and manage the interrupt safely and effectively without compromising system integrity.