Topic 7 - Fundamentals of computer organisation and architecture

The processor

Executes program instructions in order to run applications

Main memory

Stores program instructions and frequently used data

Bus

A series of parallel wires that connects internal components of a computer system, allowing signals to be passed between them

3 busses

Address bus, Control bus, Data bus

Address bus

Used to transport memory addresses, specifying where data is to be sent to or retrieved from

Data bus

Sends data and instructions to and from the different components of the computer system

Control bus

Carries control signals that regulate the operation of the computer system

Input/Output controllers

Pieces of hardware that control the communication of data between the processor and external hardware devices

Harvard architecture

Instructions and data are stored seperately

Better for embedded systems

Von Neumann architecture

Instructions and data are stored together in same memory

Better for general purpose systems

The stored program concept

Serially fetches and executes machine code instructions stored in main memory by a processor that performs arithmetic and logical operations

Processor

Executes instructions in order to run programs

Arithmetic logic unit (ALU)

Performs arithmetic and logic operations

Control unit (CU)

Controls the various components of the processor

Registers

Small storage locations used to hold data temporarily

Program counter (PC)

Used to hold the memory address of the next instruction to be executed in the FDE cycle

Current instruction register (CIR)

Holds the instruction that is currently being executed by the processor

Memory address register (MAR)

Stores the memory address of a memory location that is to be read from or written to

Memory buffer register (MBR)

Holds the contents of a memory location that has been read from or data that is to be stored

Status register (SR)

Contains a number of bits, the values of which can indicate the occurence of an interrupt

Clock

Generates a timing signal which synchronises communication between the components of the processor and the rest of the computer system

FETCH decode execute cycle

Content of PC copied to MAR

Content of MAR transferred to main memory using address bus

Instruction sent from main memory to MBR using data bus

PC incremented by 1

Content of MBR is copied to CR

fetch DECODE execute cyle

Content of CIR is decoded by the control unit

Decoded instruction split into opcode and operands

fetch decode EXECUTE cycle

Any data required that isn’t present in registers is fetched

Instruction carried out

Results are stored in registers or main memory

Interrupts in the FDE cycle

Between execute and fetch stage of FDE cycle

Content of status register is checked for changes that could signify the occurence of an interrupt

Opcode

Specifies the type of operation that is to be carried out

Operand

The pieces of data on which the operation is performed

Interrupt

A signal sent to the processor by another part of the computer requesting the attention of the processor

Factors affecting processor performance

Number of cores

Cache memory

Clock speed

Work length

Address bus width

Data bus width

How number of cores affects processor performance

Each core can perform its own FDE cycle, so more cores means more applications at once

How cache memory effects processor performance

Cache memory stores frequently used information, so the more cache means more information can be stored and accessed quickly

How clock speed affects processor performance

The higher the clock speed, the more FDE cycles can be completed in a period of time

How word length affects processor performance

A word is a group of bits treated as a single unit of data by a processor. Higher word lengths allow for more bits to be transferred and manipulated as a single unit

How address bus width affects processor performance

Increasing the width of the address bus increases the specific range of addresses that it can specify, increase the computer’s amount of addressable memory

How data bus width affects processor performance

Increasing the width of the data bus increased the volume of data that can be transferred over the bus at one time, reducing the number of FDE cycles required to fetch large volumes of data

Barcode reader

Laser shone from device

Laser hits barcode

Light is reflected off white surface and absorbed by black

Reflected laser hits sensor and is recorded

This is then converted into 1’s and 0’s where the laser has been reflected/absorbed

Digital camera

Light enters camera through lens

Lens focuses light onto sensor

Colour depends on fequency of light wave

Sensor consists of a grid and each part has its colour recorded

The data is stored in binary in a grid like pattern

Laser printer

An electron beam is fired at a negativly charged drum to create a pattern of positive charges on the drum

The drum then picks up the ink on the positive charges

The ink is then rolled onto the paper

There is a drum for each colour (CMYK)

The colours layer on top of each other

The paper is then rolled through a heat press which fuses the ink to the paper

RFID

The reader transmits data via radio waves

The energy activates the chip

The chip modulates the energy

It then transmits a signal back towards the reader

The information received by the reader is then stored and/or compared to a database