Experiment 8

Junction Field Effect Transistor

JFET stands for _

Voltage-controlled

JFET is _ (voltage or current?) controlled

Unipolar

JFET uses _ type of charge carriers

Gate, Drain, Source

Three terminals of a JFET are _

Gate

JFET control terminal (equivalent to BJT Base) is the _

Drain

JFET terminal analogous to BJT Collector is the _

Source

JFET terminal analogous to BJT Emitter is the _

VGS (Gate-Source voltage)

JFET controlling parameter is _

Reverse-biased

JFET Gate junction is _ during normal operation

0

Gate current IG in JFET is _

Very high (MΩ range)

JFET input impedance is _ compared to BJT

N-Channel, P-Channel

Two types of JFETs are _

N-type (electrons)

N-Channel JFET channel material is _

P-type (holes)

P-Channel JFET channel material is _

Electrons

N-Channel JFET majority carriers are _

Holes

P-Channel JFET majority carriers are _

Negative

N-Channel JFET VGS control range is _

Positive

P-Channel JFET VGS control range is _

Less noisy

JFET advantage over BJT in terms of noise is _

Smaller

JFET advantage over BJT in physical size is _

No offset voltage

JFET advantage: it has _

High ESD susceptibility

JFET disadvantage vs. BJT is _

Lower gain

JFET disadvantage vs. BJT in terms of gain is _

Lower (kΩ range)

BJT input impedance compared to JFET is _

Higher (β 50–300)

BJT current gain compared to JFET is _

More noisy

BJT disadvantage vs. JFET in terms of noise is _

Not ESD susceptible

BJT advantage over JFET regarding ESD is _

Reverse-biased, Forward-biased

JFET gate bias vs. BJT base bias: _ vs. _

Depletion region expansion

Gate reverse bias causes _ narrowing the channel

IDSS

Maximum drain current at VGS = 0 is called _

VP (Pinch-off Voltage)

VDS at which ID becomes constant (VGS=0) is called _

VDS(max)

Maximum VDS before breakdown is called _

Ohmic (Linear/Active)

JFET region where device acts as variable resistor is _

Saturation

JFET region used for amplification is _

Breakdown

JFET region that may destroy the device is _

Cut-off

JFET region where ID ≈ 0 is _

VDS < VP

Condition for JFET Ohmic region: _

VDS ≥ VP

Condition for JFET Saturation region: _

VGS ≤ VGS(off)

Condition for JFET Cut-off region: _

VGS(off) = −VP

Relationship between cut-off voltage and pinch-off voltage: _

Voltage-controlled resistor

JFET in Ohmic region behaves as a _

VGS controls ID

In JFET Saturation region, current is primarily controlled by _

Automatic gain control (AGC)

Ohmic region variable-resistance property used in _

lower ID

In N-Channel JFET, effect of increasingly negative VGS is _

Depletion region widens

Negative VGS on N-Channel JFET causes _

less current

Wider depletion region results in _

VGS = 0

Family of characteristic curves: IDSS reached when _

Spec sheet, diode check

JFET terminal identification methods are _

Gate

Common terminal found in JFET diode check is the _

N-Channel

Positive probe on Gate during forward bias means JFET is _

Gate-Source (GS) pair

Higher forward voltage in JFET diode check identifies the _

Source more heavily doped

Gate-Source shows higher voltage because _