digital electronics

XOR gate

either, or but NOT BOTH

XNOR gate

• inverse XOR

• if A and B are equal

• If A and B are true

• or if A and B are false

de morgans law

NOT(AB) =NOT(A) + NOT(B)

combining groups of ones in karnaugh map

sum of products (multiply them)

karnaugh map rules

1. construct largest group first

2. progressively smaller groups added

3. can overlap groups if singular one

sum of products

• for each line of truth table thats a minterm (F=1)

• multiply the variables together to get expression for that line

• then add the multiplied expressions

eg. ABC + AB

product of sums

• for each line on the truth table thats a maxterm (F=0)

• add the variables together in the row

• then multiply all the added up rows

• eg (A+B+C)(A+B)

maxterms from karnaugh map

1. group 0s and multiply groups together

2. then use de morgan law to turn multiplication into addition

order of combinations for karnaugh map

00, 01, 11, 10

NAND and NOR gates

• not what is intuitive

• think and gate and then not (01=1)

• think or gate and then not (01=0)

• so flip whetever and and or ouptut would be

making karnaugh map hazard free

create more groups of ones so there are no gaps in between original groups

static hazard reason

all real gates take a finite amount of time to operate and so produce a delay in the signals passing through them

function hazard

unsolvable hazard, occurs when more than one input variable changes at the same time

• only way to avoid is to restrict change of input variables to one at a time

binary arithmetic 1+1

=10

• write the 0 carry the 1

the thing you carry in binary arithmetic

carry = AND function

the thing you carry in binary arithmetic

“sum” = XOR function

logical depth

the max number of gates through which a signal will pass from input to output (carry and sum)

• if depth of C output = 1 and S output = 3 then C will reply before S causing hazard

1 + 1 + 1

11

10-1

1

full adder vs half adder

half adder: inputs = A, B outputs = carry, sum

full adder: inputs = A, B, carry_in outputs = carry_out, sum

11 + 1

100

hexadecimal

ends at 9 then goes A, B, C… (A = 10, B=11, C = 12)

• uses base 16 so decimal-hexadecimal is divide by 16

ones complement

just flip all the bits

• problem: gives two values for zero

twos complement

flip all the bits then add 1 to the end

adding ones complement

overflow (adding extra place at front) must be wrapped around

adding twos complement

• if the 2 last numbers u carry over are both 1 or both 0 overflow can be ignored

• if they are different then overflow cannot be ignored

sign magnitude

add sign bit to the left of biggest digit

0 = positive

1 = negative

combinational vs sequential logic

combinational: output depends only on current inputs

sequential: output depends on current inputs + previous outputs (memory)

• latches, flip flops

SR latch high input

NOR gates

SR high input set + reset

set: S = 1, R = 0, Q = 1

reset: S = 0, R=1, Q = 0

SR high input hold + forbidden

00 = hold, 11=forbidden

SR low input

NAND gates

gates r just all flipped

how does SR latch high input fix switch debouncing

• stores a stable state (hold)

• if switched to A bounce between reset and hold

• if switched to B bounce between set and hold

• reset and set switch for low input

• bouncing between hold just stays the same

SR latch with enable

E = 0 means hold doesnt matter what SR arre

E = 1 means listen to inputs

“4 bit detector”

circuit with 4 inputs

even/odd parity

• add zero to front if uneven number of 1s (for even)

• add 1 to front if uneven zeros (for odd)

parity detection

• xor all bits together using answer from last one with next

• XOR result = 0 means even 1s

• XOR result = 1 means odd 1s

BCD digit

• 1-9

• 1 is 0001 then just add that to get to 9

S-R characteristic table

11 fobridden

remeber S =1 = set

D latch basic

• one input

• S = D

• R = not(D)

if E = 0 — Q_next = Q_old (hold)

if E = 1 and D = 0 (S=0, R = 1) so Q_next = 0

if E = 1 and D =1 (S=1, R = 0) so Q_next = 1

active low D latch

enable = 0 - circuit on Q_next=D

enable =1 - circuit off Q_next = Qthe same

active low with SR latch

enable = 0 - circuit off, holds S=R =1

enable = 1 - circiut follow input S=S R=R

A + not(A)=

1

1 + A=

1

AA=

A

A(A+B)=

A

A + AB

A

AnotA=

0