8088 Assembly Language and Architecture Practice Flashcards

A comprehensive set of vocabulary flashcards covering Intel 8088 architecture, memory segmentation, register sets, instruction types, stack operations, and interrupt handling based on the lecture transcript.

Address Bus

A unidirectional bus (CPU → Memory) that carries the memory cell address the CPU wants to read or write; in 8088, it is 20 bits wide, allowing access to 1 MB ($2^{20}$ bytes).

Data Bus

A bidirectional bus (CPU ↔ Memory) that carries the actual data being read or written; in 8088, it is 8 bits wide.

Control Bus

A bidirectional bus that carries control signals such as read/write direction, interrupt signals, and bus ready signals to synchronize operations.

AX (Accumulator)

A 16-bit register used for all arithmetic/logic operations, divisible into AH (high byte) and AL (low byte).

BX (Base)

A 16-bit register used as a base address for memory access ($BX + \text{offset}$), divisible into BH and BL.

CX (Counter)

A 16-bit register used as a loop counter and shift count, divisible into CH and CL.

DX (Data)

A 16-bit register used in $MUL/DIV$ instructions for extended results, divisible into DH and DL.

SI (Source Index)

A 16-bit register that points to the source in string operations.

DI (Destination Index)

A 16-bit register that points to the destination in string operations.

SP (Stack Pointer)

A 16-bit register that points to the top of the stack; it is decremented on $PUSH$ and incremented on $POP$.

BP (Base Pointer)

A 16-bit register primarily used to access parameters on the stack.

IP (Instruction Pointer)

A 16-bit register that points to the next instruction to execute; it cannot be set directly.

CS (Code Segment)

A 16-bit register that holds the base address of the code segment.

DS (Data Segment)

A 16-bit register that holds the base address of the data segment.

SS (Stack Segment)

A 16-bit register that holds the base address of the stack segment.

ES (Extra Segment)

An extra 16-bit data segment register used as the destination in string instructions.

Zero Flag (ZF)

A flag set to $1$ if the result of an operation is zero.

Carry Flag (CF)

A flag set to $1$ if there is a carry out of the MSB, indicating unsigned overflow.

Direction Flag (DF)

Controls string instruction direction: $0$ for forward ($CLD$) and $1$ for backward ($STD$).

Interrupt Flag (IF)

Enables ($STI$, result $1$) or disables ($CLI$, result $0$) maskable interrupts.

Physical Address Calculation

Formula: $\text{Physical Address} = (\text{Segment Register} \times 16) + \text{Offset}$; also represented as $(\text{Segment Register} \text{ << } 4) + \text{Offset}$.

Paragraph Boundary

The 16-byte boundary where segments must start, meaning the lower 4 bits of a segment address are always $0$.

Little Endian Format

The storage method in 8088 where the least significant byte of multi-byte data is stored at the lower memory address.

Direct Addressing

An addressing mode where the operand is at a fixed memory address, such as $mov\text{ }ax,\text{ }[var]$.

Register Indirect Addressing

An addressing mode where the address is stored in a register like BX, SI, DI, or BP (e.g., $mov\text{ }ax,\text{ }[bx]$).

TEST Instruction

An instruction that performs a bitwise $AND$ but discards the result, updating only the flags to check bits without changing data.

SAR (Shift Right Arithmetic)

A shift operation that preserves the sign bit, used for dividing signed integers by $2^n$.

Unsigned Multiplication (MUL) 8-bit

Operation where $AX = AL \times src8$.

Unsigned Multiplication (MUL) 16-bit

Operation where $DX:AX = AX \times src16$, resulting in a 32-bit product.

Unsigned Division (DIV) 8-bit

Operation where $AL = AX \text{ } \text{/} \text{ } src8$ (quotient) and $AH = AX \text{ } \text{mod} \text{ } src8$ (remainder).

Unsigned Division (DIV) 16-bit

Operation where $AX = DX:AX \text{ } \text{/} \text{ } src16$ (quotient) and $DX = DX:AX \text{ } \text{mod} \text{ } src16$ (remainder).

CMP Instruction

Performs subtraction ($\text{dest} - \text{src}$) and discards the result, updating only the flags for conditional branching.

LOOP Instruction

A counter instruction that decrements $CX$ by $1$ and jumps to a label if $CX \neq 0$.

Stack

A Last-In, First-Out (LIFO) data structure that grows downward in memory from high addresses to low addresses.

CALL Instruction

Automatically pushes the return address ($IP + \text{instruction size}$) onto the stack and jumps to the subroutine.

RET Instruction

Pops the return address from the stack back into the $IP$, resuming execution after a $CALL$.

Near Call

A call where the target is in the same code segment, pushing only the 2-byte $IP$ onto the stack.

Far Call

A call where the target is in a different code segment, pushing both the 2-byte $CS$ and 2-byte $IP$ (4 bytes total) onto the stack.

Display Memory Base Address

In text mode, the physical address $0xB8000$ (segment $B800h$) where the screen is mapped.

Screen Position Formula

Formula used to locate a character in display memory: $\text{Offset} = (\text{row} \times 160) + (\text{column} \times 2)$.

Attribute Byte

The second byte of a character in display memory that defines color (Blink, Background, Bright/intensity, Foreground).

MOVSB / MOVSW

String instructions that move a byte or word from $[DS:SI]$ to $[ES:DI]$ and adjust pointers based on the $DF$.

REP Prefix

A prefix used with string instructions to repeat the operation $CX$ times.

Interrupt Vector Table (IVT)

A 1 KB table at $0x00000$ containing 256 far pointers (4 bytes each) to Interrupt Service Routines (ISRs).

IRET

The instruction used to end an ISR, which pops the $IP$, $CS$, and $FLAGS$ from the stack to resume the original program.

IRQ 0

The System Timer hardware interrupt ($INT\text{ }0x08$) which fires approximately $18.2$ times per second.

PIC (8259)

The Programmable Interrupt Controller that manages hardware interrupt lines known as IRQs.

EOI (End Of Interrupt)

The signal ($0x20$) that must be sent to the PIC command port ($0x20$) at the end of a hardware ISR to allow further interrupts.