Computer Architecture

Computer Architecture Definition

specification of a set of instructions and the specification of the behaviour of hardware units to implement/support these instructions

Instruction Set Architecture Definition

The conceptual structure and functional behavior of a computer system as seen by the assembly-language programmer, including machine instructions and their formats, addressing modes, data representation, and storage organization.

Parts of a Processor

Processor-memory interface, Arithmetic Logic Unit, Registers, Control, Program Counter, Instruction Register

Addressing modes

Immediate: e.g. movi, addi

Register: e.g. mov

Absolute: EA = LOC - cant put whole address, it wont fit in the instruction size

Index: EA = offset(R) e.g. load, store

Parts of a computer

Memory, Control, ALU, Input, Output

How many registers are there

32

Special Registers

31: link register (except for us its r8)

27: stack pointer

0: zero register, always holds 0

Program Counter

Holds the address of the next instruction

Instruction Register

Holds the next instruction

Control Unit

coordinates fetches, retrieves, logic computations, reads, and writes

receives state signals and sends timing signals to/from units

often distributed throughout the computer

ALU

holds the circuitry to do combinational logic and arithmetic

Processor Memory Interface

a collection of wires that carry reads, writes, and signals

size of a word

32 bits, 4 bytes

Generic Instructions

Load, Add, Store, Subtract, Move

What does RISC stand for

Reduced Instruction Set Completion

size of RISC instructions

32 bits

Machine Instruction

a command specifying a data transfer or arithmetic/logic operation

Types of Memory

Primary memory(RAM, Cache), Secondary Memory

Primary Memory

uses semiconductor storage cells (fast)

includes RAM, and Cache

Cache

stores current/recent program instructions and data. on same chip as processor

RAM

has fixed access time that is independent of location

Secondary Memory

larger capacity that holds info when computer is off. Less expensive, but slower

Big-Endian

lower addresses hold more significant (leftward) bits

Little Endian

lower addresses hold less significant (rightward) bits

Read

memory retrieves contents at address given by processor

Write

memory overwrites contents at given location with given data

steps for fetching an instruction

send pc value to memory as address

command memory to perform a read

increment PC value by 4 inside processor

place result from memory in IR

T/F calls are included in branching

T: though they are not branch instructions

What happens in branching

PC is updated to point to the instruction after call

that address is saved to the link register

then it is overwritten with the target address

how do addresses fit in instructions

remove 2 lowest bits (always 0 since multiple of 4), get rid of 4 highest bits

first instruction for the stack pointer

movia sp, 0×7FFFFC

Shifts

multiply / divide by 2

logical and arithmetic (preserves sign bit)

steps of movia

OrHigh - moves top 16 bits

Or - adds last 16 bits

3 lines of startup code

.text

.global _start

.org 0×0

Steps in Calls and Returns

Call:

copy PC value to Link Register

reconstruct target address by adding 2 zeros to the end and copying the highest 4 digits from PC to the front

copy subroutine address in IR to PC

Return: copy link register contents to PC

general steps to process any instruction

fetch, decode/interpret, execute