CS132 - Memory Systems
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98 Terms
List the memory hierarchy from fastest/smallest to slowest/largest.
Registers, cache, main memory, secondary storage, archival storage.
Why is the memory hierarchy needed?
No single memory type is fast, large, cheap and low-power at once, so frequently used data is kept in faster smaller memory.
What is temporal locality?
If data is used now, it is likely to be used again soon.
What is spatial locality?
If data at one address is used, nearby addresses are likely to be used soon.
What are registers?
Very small, very fast storage locations inside the CPU, used for operands, addresses and temporary results.
What is cache?
Fast memory between CPU and main memory that stores recently or likely-to-be used data.
What are L1, L2 and L3 cache?
Cache levels; L1 is smallest/fastest, L2 larger/slower, L3 larger/slower again.
What is cache usually made from?
SRAM.
What does cache being transparent to the programmer mean?
The programmer normally does not manually decide what goes in cache.
What is a cache hit?
The required data is found in cache.
What is a cache miss?
The required data is not in cache and must be fetched from a lower memory level.
Hit rate formula?
Hit rate = cache hits / total memory references.
Miss rate formula?
Miss rate = 1 - hit rate.
AMAT formula?
AMAT = hit time + miss rate * miss penalty.
What is a compulsory cache miss?
A miss because the data has never been loaded into cache before.
What is a capacity cache miss?
A miss because cache is too small to hold all needed data.
What is a conflict cache miss?
A miss caused by the cache placement strategy forcing useful data to be replaced.
What is a coherency cache miss?
A miss because data was changed elsewhere, so the cache copy is invalid.
Write-through vs write-back cache?
Write-through updates cache and lower memory immediately; write-back updates cache first and lower memory later when the block is replaced.
Write-through advantage and disadvantage?
Advantage: main memory stays up to date. Disadvantage: slower and more memory traffic.
Write-back advantage and disadvantage?
Advantage: faster repeated writes and less traffic. Disadvantage: more complex and main memory may be temporarily out of date.
What is main memory?
Larger, slower memory that stores programs/data not currently in registers/cache, usually DRAM.
What does SRAM stand for?
Static Random Access Memory.
What does DRAM stand for?
Dynamic Random Access Memory.
SRAM vs DRAM?
SRAM is faster, expensive, lower density, no refresh, used for cache. DRAM is slower, cheaper, higher density, needs refresh, used for main memory.
How does SRAM store data?
Using latch-like circuits, often around 6 transistors per bit.
How does DRAM store data?
As charge in a capacitor, usually with 1 transistor and 1 capacitor per bit.
Why does DRAM need refreshing?
Capacitors leak charge over time.
What is a memory array?
A 2D arrangement of memory cells with rows selected by addresses and columns/data lines providing word width.
Memory array size from address bits and width?
With N address bits and M data bits per address: 2^N rows and total size 2^N * M bits.
What are memory depth and width?
Depth is number of addressable rows; width is number of bits per row/word.
How many rows do 10 address bits select?
2^10 = 1024 rows.
What does a memory decoder do?
It converts address bits into one selected wordline/row.
What happens when you add one address bit?
The number of addressable locations doubles.
Why split addresses into row and column parts?
It reduces decoder complexity and can reduce external address pins.
A 16-bit address, 1-bit-wide memory stores how much data?
2^16 bits = 65,536 bits = 8,192 bytes = 8 KiB.
How do 3 extra address lines expand memory using identical chips?
Feed the 3 extra lines into a 3-to-8 decoder. Each output is a chip-select for one chip. Original address lines go to all chips; only one chip is enabled.
If 3 extra address lines select identical 16-bit-address 1-bit chips, total capacity?
8 * 65,536 bits = 524,288 bits = 65,536 bytes = 64 KiB.
How do you make 1-bit memory chips support parallel byte read/write?
Place 8 chips side by side sharing address lines. Each chip outputs one bit, giving 8 bits in parallel.
What is an SSD?
Solid State Drive using non-volatile flash memory.
What is erase-before-write in flash?
Flash is read/written in pages but erased in larger blocks, so updated data is often written elsewhere and cleaned later.
Name three SSD problems.
Retention loss, limited lifetime/program-erase wear, and multi-level cells being more error-prone.
What is an HDD?
Hard Disk Drive storing data by magnetising regions on spinning disks, read by a moving read/write head.
What are HDD tracks and sectors?
Tracks are circular paths on the disk; sectors are subdivisions of tracks containing data blocks.
Do HDDs use error correction?
Yes. Sectors usually store ECC bits.
What four factors determine HDD access time?
Seek time, rotational latency, settle time, and read/write time.
What is seek time?
Time to move the head/arm to the correct track.
What is rotational latency?
Time waiting for the correct sector to rotate under the head.
What is settle time?
Time for the head/arm to stop vibrating after movement.
What is read/write time?
Time to actually transfer the data once the head is positioned.
What is an alternative to Return to Bias magnetisation?
Transition-based recording, where changes in magnetisation represent bits.
Why can transition-based magnetisation be better than Return to Bias?
Transitions are easier for the read head to detect reliably than absolute magnetic direction.
What is noise in memory/data transfer?
Unwanted interference that can flip bits from 0 to 1 or 1 to 0.
What is EDC?
Error Detection Code: detects that an error occurred but cannot fix it by itself.
What is ECC?
Error Correction Code: detects errors and uses redundant information to reconstruct correct data.
Give examples of EDC.
Parity bit, checksum, CRC.
Give examples of ECC.
Hamming codes and Reed-Solomon codes.
What is a parity bit?
An extra bit added so the total number of 1s is even or odd.
How do you calculate even parity?
Count the 1s. Add parity bit 1 if the count is odd, or 0 if the count is already even.
How do you calculate odd parity?
Count the 1s. Add parity bit 1 if the count is even, or 0 if the count is already odd.
What can simple parity detect?
Single-bit errors and any odd number of bit flips.
Why can parity fail?
An even number of bit flips can leave the overall parity looking correct.
How can parity be checked quickly in hardware?
Use XOR gates over all data bits and the parity bit.
How would you store parity per byte in memory?
Add one extra parity bit per 8 data bits, so each byte needs 9 stored bits. Use XOR gates to generate parity on write and check it on read.
What is 2D parity?
Data is arranged in rows and columns with parity bits for each row and column.
Why is 2D parity better than simple parity?
It gives stronger detection and can locate/correct a single-bit error using the failing row and column.
What is a Hamming code?
An ECC code that adds redundant check bits so a single-bit error produces a unique syndrome identifying the faulty bit.
What is Hamming(7,4)?
A Hamming code with 4 data bits and 3 check bits, giving 7 bits total.
Parity vs 2D parity vs Hamming code?
Parity is simple detection only; 2D parity can locate a single-bit error in a block; Hamming can correct single-bit errors within a word.