GCSE Computer Science: Internal & External Hardware

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Last updated 11:45 PM on 4/19/26
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41 Terms

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Accumulator (registers)

A register which intermediate arithmetic and logic results are stored

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Actuator

A mechanical device for moving or controlling a mechanism or system and controlled by a computer system

<p>A mechanical device for moving or controlling a mechanism or system and controlled by a computer system</p>
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ALU

Performs arithmetic calculations. All inputs & outputs must pass through here. Acts as a gateway to the CPU.

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Back Up

A copy of files to prevent loss of data.

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Base

The number of digits used within a number system

<p>The number of digits used within a number system</p>
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Binary

Base 2 number system which can be read by computers

<p>Base 2 number system which can be read by computers</p>
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BIOS

Basic Input Output System

<p>Basic Input Output System</p>
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CIR (registers)

The instruction in the MDR is now copied to the CIR, and then held whilst being read and executed.

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Control Unit

The CU manages the execution of instructions in a processor.

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CPU

The processor unit which carries out the fetch,decode, execute cycle using registers and busses

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Data Bus

Carries the data from one register to another.

<p>Carries the data from one register to another.</p>
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Hard Wired

Devices that are connected to a computer with cables.

<p>Devices that are connected to a computer with cables.</p>
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Hardware

The physical components that make up the computer i.e. mouse or printer etc.

<p>The physical components that make up the computer i.e. mouse or printer etc.</p>
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Immediate Access Store

AKA Memory Unit. Refers to the collective term of RAM and ROM

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Internal Memory

AKA Memory Unit. Refers to the collective term of RAM and ROM

<p>AKA Memory Unit. Refers to the collective term of RAM and ROM</p>
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MAR (registers)

Memory Address Register. Holds the address that was read from the PC.

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MDR (registers)

Memory Data Register. The contents of the address in the MAR is then stored in the MDR.

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Memory Unit

Also known as memory or Immediate Access store (IAS) refers to the collective term of RAM and ROM

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Primary Memory

Often referred to simply as memory, is the only one directly accessible to the CPU. Primary Memory is often volatile.

<p>Often referred to simply as memory, is the only one directly accessible to the CPU. Primary Memory is often volatile.</p>
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RAM

Random Access Memory. The data disappears if the power is switched off, RAM is volatile

<p>Random Access Memory. The data disappears if the power is switched off, RAM is volatile</p>
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Secondary Storage

A device that stores data for a long period of time i.e. hard drive

<p>A device that stores data for a long period of time i.e. hard drive</p>
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NOT Gate

A logic gate used to identify a true value when a condition is not met.

<p>A logic gate used to identify a true value when a condition is not met.</p>
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AND Gate

A logic gate used to identify a true value when two or more conditions are met.

<p>A logic gate used to identify a true value when two or more conditions are met.</p>
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OR Gate

A logic gate used to identify a true value when one or more conditions are met

<p>A logic gate used to identify a true value when one or more conditions are met</p>
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GPU

CPU for the Graphics Card which is optimised to produce high quality 3D graphics. This takes the strain away from the main CPU. It is known as a co-processor.

<p>CPU for the Graphics Card which is optimised to produce high quality 3D graphics. This takes the strain away from the main CPU. It is known as a co-processor.</p>
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CPU Core

One of a number of processing units inside the CPU. Common to go up in powers of 2

<p>One of a number of processing units inside the CPU. Common to go up in powers of 2</p>
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Clock Speed

Indicates how fast the processor is running. Measured in megahertz or gigahertz.

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2 Billion Cycles per Second

This is how many processes a 2GHz processor can complete. A process is a full cycle of the Fetch Decode Execute Cycle

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Fetch Decode Execute

The cycle which refers to how a Von Neumann Architecture processor receives instructions & data, then processes the instruction.

<p>The cycle which refers to how a Von Neumann Architecture processor receives instructions &amp; data, then processes the instruction.</p>
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Cache

A very small, but very fast piece of memory which is part of the CPU. It temporarily holds instructions and data that are ready to be processed.

<p>A very small, but very fast piece of memory which is part of the CPU. It temporarily holds instructions and data that are ready to be processed.</p>
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CISC

This is a processor which holds a complex instruction set which is generally larger & run at a higher clock speed. They are better at processing graphic intensive tasks.

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RISC

This is a processor which holds fewer instructions and is more energy efficient. However, they run at a lower clock speed and can be smaller which allows them to be used in smartphones & tablets.

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Motherboard

A circuit board which allows the CPU to physically connect to all other hardware in the computer system.

<p>A circuit board which allows the CPU to physically connect to all other hardware in the computer system.</p>
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Buses

Circuits within the motherboard that facilitate the transfer of data.

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Address Bus

Ciruits which send information about where data needs to go. Is sent from the CPU to the RAM

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Bridge

Direct connections between pieces of hardware on the motherboard. Divided into North & South.

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Volatile Memory

Memory which only retains data whilst the power is switched on.

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Non-Volatile Memory

Memory which retains data even when the power is switched off.

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Virtual Memory

When a section of the hard drive is partitioned and used as if it were RAM.

<p>When a section of the hard drive is partitioned and used as if it were RAM.</p>
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Latency

The time it takes for components / a server to respond to a request. There will always be a short delay to allow for the FDE cycle

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Lag

An unacceptable latency time which allows the user to be made aware of the delay in a request response.

<p>An unacceptable latency time which allows the user to be made aware of the delay in a request response.</p>