Computer Architecture - Unit I: System Bus and Organization

These flashcards cover Unit I concepts including system bus types, bus arbitration methods, memory transfer operations, CPU register organization, stack operations, and various addressing modes.

System bus

A communication highway that facilitates data and control signal transfer among components, such as the CPU, Memory, and Interface (labeled as Infarct in diagram), for information exchange.

Address bus

A unidirectional bus that carries memory addresses; its size defines the maximum addressable memory (e.g., a 32-bit address bus can access $2^{32}$ or 4 gigabits).

Data bus

A bidirectional bus that transmits data between the CPU, memory, and peripherals; its size specifies data transmission capacity (e.g., 8-bit, 16-bit, 32-bit, or 64-bit).

Control bus

A bus that transmits control signals for coordinating activities, including Read (RD), Write (WR), Clock (CLK), and Interrupt request (IRQ).

Single-shared bus

An architecture where all components share a single communication pathway, offering simplicity in design and lower cost but potential for congestion.

Multiple Shared Buses

An architecture where different components use separate communication pathways to reduce congestion and allow faster communication, though with higher complexity and cost.

Bus arbitration

A mechanism that decides the selection of a current master to access the bus when multiple units concurrently request access, usually giving priority to the master with the highest priority.

Daisy chaining method

A bus arbitration method where all masters use the same line for requests and the bus grant signal seriallly propagates through each master until it reaches the requesting one.

Polling method

A bus arbitration method involving sequentially checking each master to determine readiness; it allows priority changes by altering the polling sequence but introduces overhead.

Independent request (Fixed Priority Method)

A technique providing a unique pair of bus request and grant lines to each master, utilizing a built-in priority decoder for quick responses.

Reading (Memory Transfer)

The operation of transferring a copy of data from a memory location to the CPU.

Writing (Memory Transfer)

The operation of transferring information from the CPU to a specific memory location, replacing the previous content.

Address Register (AR)

A register that holds the memory location address from which data is to be read or where data is to be written.

Data Register (DR)

A register used to temporarily store data being transferred between memory and the CPU.

General Register-Based CPU Organisation

An organization using multiple general-purpose registers instead of a single accumulator, enabling efficient storage and reducing memory references.

Reduced Instruction Set Compacting (RISC)

A processor architecture where general register-based organization is common, supporting efficient data manipulation.

Register Stack

An ordered set of elements with variable length, also known as a pushdown list or Last-In-First-Out (LIFO) list, accessible one element at a time from the top.

Stack Pointer Register (SP)

A register containing a 6-bit binary value (ranging from $000000$ to $111111$) representing the address of the top of the stack.

FULL Register

A 1-bit register set to $1$ when the stack is full and $0$ otherwise.

EMPTY Register

A 1-bit register set to $1$ when the stack is empty and $0$ otherwise.

Memory stack

A dynamic data structure in RAM that manages subroutine control flow, return addresses, arguments, and local variables.

Addressing mode

A technique used to specify how operands are chosen for instructions, determining how the processor references memory.

Immediate Addressing Mode

A mode where the operand is specified explicitly in the instruction, such as \text{MOV AX, #5}.

Register Addressing Mode

A mode where the operand is the content of a register, such as $\text{ADD BX, CX}$.

Direct Addressing Mode

A mode where the operand is the content of a memory location directly specified by the instruction, such as $\text{MOV AX, [1000]}$.

Indirect Addressing Mode

A mode where the operand address is stored in a register or another memory location, such as $\text{MOV AX, [BX]}$.

Indexed Addressing Mode

A mode where the operand is found at the sum of a base register and an index register, such as $\text{MOV AX, [SI + 100]}$.

Relative Addressing Mode

A mode where the operand location address is the sum of a register's address and a constant offset, often used for conditional jumps.

Stack Addressing Mode

A mode where the operand is implicitly the top of the stack, such as $\text{PUSH AX}$.

Displacement Addressing Mode

A mode where the effective address is the sum of the base register $\text{BX}$ and a displacement value, such as $\text{MOV AX, [BX + 10]}$.Address = Base register + Displacement.

Implied Addressing Mode

A mode where operands are specified implicitly in the instruction definition, such as zero-address instructions in stack-organized computers.