17: Transient execution attacks

Out of order execution

• Key performance optimisation next to speculative execution

• Hides/minimises latency (eg cache misses, FPU operations)

• Keeps elements in execution pipeline busy

• Leaves data in cache(!)

What does out of order execution exploit?

• In microarchitecture. instructions can be reordered

• Usually no issue when there are no data dependencies

• Results are only committed (architecturally) once all operations are completed

Common techniques for suppressing faults

• Custom segfault handlers

• Intel’s Transactional Synchronisation Extensions (TSX)

Meltdown

• Need to architecturally suppress faults

Intel’s Transactional Synchronization Extensions (TSX)

• ISA extension for hardware transactional memory

• Allow parallelism via lock elision

• Data accesses are bundled in transactions

• If transaction fails:

  • Re-roll and try again (HLE)

  • Jmp to custom handler (RTM)

• Now disabled for desktop CPUs, still available one some Xeon CPUs

Spectre

• Abuses branch (mis)prediction and speculative execution

  • Access sensitive data transiently

  • Cache side-channel to exfiltrate data

• Full class of attacks

  • New variants are still discovered

  • Previously thought mitigated issues turn out to still be exploitable

  • Still an active research topic

Spectre-v1 (Spectre-PHT) attack steps

• Train direct branch predictor to take branch

• Execute target with x out of bounds

  • This will transiently access the value at array1[x]

• Exfiltrate secret via cache side channel by probing array2

  • eg via flush + reload

Spectre impact

• Almost every CPU before 2018 vulnerable

  • Software and microcode mitigations

  • Partially high performance impact

Newer CPUs

Have hardware mitigations against some variants of Spectre

Meltdown is fully mitigated in

Hardware

Spectre hotfixes and workarounds

• Intermediate solution found after vulnerabilities

• Implemented by:

  • Removing particular gadgets used during attacks

  • Changes to software

  • Microcode updates to disable features or change instruction behaviour

Spectre hotfix advantages

Fast mitigation of specific attack vector

Spectre hotfix disadvantages

Performance overhead and may not fully mitigate attacks

Hardware defenses

• Take time to develop - CPU design-release cycle takes multiple years

• Sometimes allow to fully remove vulnerability

• May not be complete (for performance reasons)

Systematic defenses

• Less used in practice

• High performance overhead

• Major software changes needed

Transient execution

• Changes microarchitectural state

• Even if results are not used architecturally, it leaves traces in the microarchitecture

• Attackers can use this to leak information across privilege domains via side channels

Spectre type

Speculation based

Meltdown type

Exception based