EECS 31L midterm 2 prep

module / endmodule

Defines a hardware block; top-level unit in Verilog

input / output / inout

Port direction declarations

wire

Continuous-value net driven by assign or module output; cannot store state

reg

Variable that holds its value until reassigned; used inside always/initial blocks

parameter

Compile-time constant that can be overridden at instantiation

localparam

Compile-time constant that cannot be overridden externally

genvar

Elaboration-time loop variable; NOT a signal; cannot be used in simulation

generate / endgenerate

Wraps generate constructs (for loops, if, case)

always

Procedural block that re-executes whenever sensitivity list changes

initial

Procedural block that executes once at time 0; used in testbenches

assign

Continuous assignment; drives a wire; always active

case / endcase

Multi-way branch; matches exact value (4-state: 0, 1, X, Z)

casex

Case with don't-care matching on X and Z

casez

Case with don't-care matching on Z only

begin / end

Groups multiple statements into a block

Positional mapping

Port connections by order; matches declaration sequence in module definition

Named mapping

Port connections by name using .port_name(signal) dot notation

Elaboration

Pre-simulation phase where generate loops are unrolled and hierarchy resolved

Simulation

Runtime phase where signals have values and time advances

Opcode

Binary control signal that selects which ALU operation to perform

ALU

Arithmetic Logic Unit; combinational circuit that performs arithmetic/logic ops

Multiplexer (Mux)

Selects one of many inputs based on a control signal

Register File

Array of registers with read and write ports; used to store operands

Read port

Port that outputs a register value given an address

Write port

Port that writes a value to a register at a given address

Address bus

Set of wires used to select a register; width = log2(number of registers)

Data bus

Set of wires that carry data to/from registers; width = word size

Word size

Bit-width of each register in the file

Zero flag (Z)

Output flag; 1 when ALU result equals 0

Negative flag (N)

Output flag; equals MSB of ALU result

Parity

XOR of all bits; 1 if odd number of 1s, 0 if even