Active Recall for 143

Describe the operational behavior of an Exclusive OR (XOR) gate

An XOR gate produces a logic high (1) output if and only if its inputs are different from each other. If the inputs are identical, the output is a logic low (0).

Give both forms of De Morgan's theorem

(A.B.C.D)’ = A’ + B’ + C’ + D’
(A + B + C + D)’ = A’.B’.C’.D’

Briefly describe when "don't care" states may be used when designing logic circuits.

"Don't care" states are used when certain input combinations are physically impossible or guaranteed to never occur in the system's operation. In K-map simplification, they are highly advantageous because they can be flexibly treated as either a 1 or a 0 to help construct the largest possible groupings, thereby yielding the minimum/simplest logical expressions.

Describe Moore's Law and outline the reasons for its success in driving advancements in electronics.

Moore's Law states that the number of transistors on a microchip doubles roughly every two years, exponentially decreasing manufacturing costs per transistor. Its massive success was driven by smaller transistors operating at faster switching speeds, lower dynamic power consumption, and its role as an aggressive commercial roadmap for the global semiconductor industry.

nMOS Inverter VTC Regions

When the input is low (V_in < V_T), the driver transistor is in Cut-off, pulling the output up to its highest voltage (V_OH). When the input is high, the driver switches into the Linear region, dropping the output to its lowest level (V_OL), while the permanently saturated load transistor acts as a high-resistance pull-up.

Active Loads vs Passive Loads

Passive resistor loads consume an enormous physical area on a silicon chip to achieve high resistance values. Replacing them with an active load transistor minimizes physical layout area, provides a much higher effective resistance, and establishes steeper switching curves that deliver superior voltage gains.

CMOS Inverter Advantages

CMOS designs switch between a complementary pair of p-channel and n-channel transistors, meaning one device is always fully off during steady states. This completely eliminates direct current paths from V_DD to Ground, reducing static power dissipation to near zero and allowing the output voltage to swing fully rail-to-rail.

p-n Junction & Depletion Layer

A p-n junction forms a metallurgical boundary when a hole-rich p-type semiconductor contacts an electron-rich n-type semiconductor. Mobile carriers spontaneously diffuse across this boundary and recombine, leaving behind fixed, immobile charged ions that create a carrier-free "depletion layer" with an internal electric barrier.

p-n Junction Under Bias

Forward bias opposes the internal barrier, narrowing the depletion layer to allow an exponential flow of diffusion current across the device. Reverse bias reinforces the internal field, widening the depletion region and blocking carrier flow, leaving only a tiny, negligible minority carrier leakage current.

MOS Capacitor Applications

The MOS structure is primarily used as the foundational gate-control stack that regulates the channel in all modern MOSFET transistors. Additionally, it serves as the tiny storage cell to hold bits of charge in dynamic memory (DRAM) and traps photogenerated charges within digital camera imaging arrays (CCDs).

MOS Capacitor Conditions (n-type)

Positive gate voltages create Accumulation by pulling bulk electrons right up to the oxide interface (C_T = C_ox). Negative gate voltages push electrons away to form Depletion (C_T drops), which eventually transforms into Inversion under strong negative bias, where a permanent p-type layer forms beneath the oxide. At high frequencies, total capacitance stays frozen at its absolute minimum because slow minority carrier holes cannot react fast enough to the changing signal.

Combinational vs. Sequential Logic Circuits

Combinational logic is time-independent; its output at any given instant depends strictly on the input combinations present at that exact moment. In contrast, sequential logic circuits possess memory, meaning their output values depend on a combination of both present inputs and historical past states.

Propagation Delay & Circuit Glitches (Hazards)

Propagation delay is the finite fraction of a second required for a digital signal to physically travel from a gate's input to its output. A glitch (circuit hazard) occurs when unequal propagation paths cause converging logic inputs to change states at slightly different times, forcing the final output to momentarily drop to an incorrect logic state.

Ring Oscillators

A Ring Oscillator is formed by connecting an odd number of NOT gates in a closed serial chain, feeding the last output back to the first input. Lacking any single stable state, the circuit oscillates continuously between states and is actively used to experimentally measure internal gate propagation delays (𝛕).

Latch Transparency & The Master-Slave Concept

Standard clocked latches are transparent, meaning any input fluctuation instantly alters the output while the clock is active, which causes errors in shift registers. The Master-Slave configuration solves this: the master latch is transparent when the clock is high, but the slave isolates the system and updates the final output only when the clock drops low.

Synchronous vs. Asynchronous Sequential Circuits

Synchronous circuits connect a single, universal clock signal directly to every internal flip-flop, forcing all outputs to change state at the exact same instant to eliminate hazards. Asynchronous (ripple) circuits do not share a common clock, meaning outputs switch sequentially one after another, introducing unwanted propagation delays and glitches.

MOSFET Scaling Benefits (Dennard Constant-Field Scaling)

Scaling down lateral and vertical dimensions by a factor of $k$ allows microchips to pack more components onto a single die. This process boosts packing densities, increases manufacturing yield to lower unit costs, and minimizes gate channel delays to deliver faster overall operational speeds.

Scaling Bottlenecks: Short-Channel Effects (SCE)

As the gate length (L) shrinks to atomic nanometer scales, the source and drain depletion zones naturally draw closer together. This proximity compromises the gate's ability to electrostatically control the underlying channel, causing parasitic leakage currents to flow even when the transistor is turned off.

High-k Dielectric Solutions

Ultra-thin silicon dioxide layers (t_ox) suffer from excessive quantum tunnelling leakage currents. Replacing SiO_2 with alternative High-k dielectrics (like Hafnium Oxide) permits a physically thicker insulating layer that blocks tunnelling current while maintaining identical gate capacitance control.

Manufacturing Yield vs. Silicon Defects

Silicon wafers always contain a baseline density of localized atomic defects or processing deformations. Scaling down individual chip dimensions ensures that these static defects knock out only a few tiny dies per wafer (Case 2, high yield) rather than ruining large sections of material (Case 1, low yield)