digital electronics final review

binary counting and number systems

• Binary uses powers of 2

• Each bit position has a place value

• To convert binary to decimal, add the place values where the bit is 1

• A circuit with n flip-flops can represent 2^n states

frequency

the number of cycles per second

period

the time for one complete cycle

duty cycle

percent of the period that the signal is high

ampltitude

magnitude of a signal

high time

the time during which a waveform is 1 (high)

low time

the time during which a waveform is 0 (low)

rising edge

digital transition from low to high state

falling edge

digital transition from high to low state

frequency formula

1 / T (T=period)

period formula

T = 1/f (f=frequency)

frequency and period are..

opposites

555 timer in astable/oscillator mode

• A 555 timer in astable mode creates a repeating square wave

• Resistors and capacitors control the timing

• Increasing resistance or capacitance usually lowers the frequency

• The 555 timer can act as a clock source for counters and sequential circuits

duty cycle formula

(RA + RB) / (RA + 2RB) 100%
**might have to convert values for a formula but not sure yet

series circuit traits

• Current is the same everywhere

• voltage splits across components

• total resistance adds directly

RT = r1 + r2 + r3 + …

parallel circuit traits

• voltage is the same everywhere

• current splits across components

• total resistance is less than smallest branch

1/rt = (1/r1) + (1/r2) + (1/r3)…

ohm’s law

V = IR

rearranged: I = V/R

R = V/I

I = current

V = voltage

R = resistance

voltage dividers

• voltage divider uses two series resistors to reduce voltage

• total resistance: RT = R1 + R2

• current: I = VS / RT

• voltage divider formula: VS x R2 / (R1 + R2)

and gate

1 only when all inputs are 1

or gate

1 when at least one input is 1

not gate

inverts the input

nand gate

inverse of AND

NOR gate

inverts the input

XOR gate

1 when inputs are different

XNOR gate

1 when inputs are the same

boolean expressions and k-maps

• boolean expressions describe logic circuits using variables and operators

• k-maps are used to simplify boolean expressions

• groups must be powers of 2:

  • 1, 2, 4, 8, 16

• groups may wrap around edges

• larger valid groups usually produce simpler expressions

seven segment displays

• seven-segment displays use segments labeled A through G

• each digit is created by turning on a specific combination of segments

• common cathode displays usually turn on w logic HIGH

• common anode displays usually turn on the logic LOW

• resistors limit current and protect the display

adders and two complement

• adders perform binary addition

• half adders add two bits

• full adders include a carry-in

• two’s complement is used to represent signed binary numbers

• in an 8-bit two’s complement number

  • leftmost bit 0 means positive

  • leftmost bit 1 means positive

how to decode negative two’s complement number

• invert the bits

• add 1

• convert to decimal

• add the negative sign

flip flops

• flip flops store one bit of information

• flip flops change state based on clock signals

• sequential logic depends on both inputs and stored state

counters

• counters are built from flip-flops

• each flip flop adds one binary bit

• a counter w n flip flops has 2^n possible states

• reset or control logic can limit the count range

• mod number tells how many states the counter

synchronous and asynchronous counters

Synchronous counters:

• Also called parallel counters.

• All flip-flops share the same clock.

• Faster and more predictable.

• Require more logic.

Asynchronous counters:

• Also called ripple counters.

• First flip-flop receives the external clock.

• Later flip-flops are triggered by previous flip-flop outputs.

• Simpler wiring.

• Slower due to propagation delay.

plds, programmable logic devices

advantages:

• easier to modify

• easier to test alternate designs

• less dependent on individual gate count

• less dependent on individual flip-flop count

• cleaner than large discrete-logic circuits

state machines

• a state machine moves through defined states

• each state represents a system condition

• state transitions are controlled by inputs and clock events

• each state must be assigned a binary code

• the number of flip flops depends on number of states

• formula: smallest n where 2^n is at least the number of states

how to find the number of flip flops needed

a counter must represent values up to 100

• 2^64, too small

• 2^7 = 128 is enough

• answer: 7 flip flops needed

series vs parallel behavior

add a resistor in a series circuit, then total resistance increases

however, add a resistor in parallel circuit, total resistance decreases

synchronous vs. asynchronous counters

• if every flip-flop receives the same clock, it is synchronous

• if the clock signal passed from one flip flop to the next, it is asynchronous

• propagation delay is the key weakness of asynchronous counters

binary to decimal conversion steps

• Step 1: Multiply each digit of the Binary number with the place value of that digit, starting from right to left i.e. from LSB to MSB. 

• Step 2: Add the result of this multiplication and the decimal number will be formed.

sequential logic

logic in which outputs depend on current inputs and stored past state

memory

the ability of a circuit to store information over time

latch

a level-sensitive storage device whose output can change while enabled

flip flop

an edge triggered storage device that updates only a clock transition

clock

a periodic signal that controls when flip flops update

positive edge

the transition from 0 to 1 on a clock signal

negative edge

the transition from 1 to 0 on a clock signal

asynchronous input

an input that affects output immediately, independent of the clock

synchronous input

an input that affects output only on a clock edge

d flip flop

a flip flop where the output copies the D input on clock edge

J/K flip flop

a flip flop that can set, reset, hold, or toggle

toggle

a behavior where the output switches state on each clock edge

divide by two

a circuit that outputs a frequency half of the input clock

event detection

using memory to record that an input event occurred

duty cycle

the percentage of time a signal is high during one period

sequential logic systems

• outputs depend on inputs plus stored state

• memory elements are required

• clocked operation makes behavior predictable

latches vs flip flops

• latches respond to levels

• flip flops respond to edges

• unit 3 circuits use flip flops only

d flip flop

Behavior

• On the active clock edge:
  Q ← D

• Between clock edges:
  Q holds its value

Inputs

• CLK (edge-triggered)

• PRE (preset), asynchronous, active low

• CLR (clear), asynchronous, active low

synchronous vs asynchronous inputs

synchronous

• evaluated only on clock edges

• predictable and controlled

asynchronous

• Act immediately.

• Override normal operation.

• Must be used carefully.