Digital Integrated Circuits: CMOS Logic, Delay Optimization, Sequential Elements, and Semiconductor Memories

Comprehensive vocabulary flashcards covering static CMOS logic, delay models, logical effort, timing constraints in sequential circuits, transmission gates, dynamic domino logic, and semiconductor memory design (SRAM, DRAM, and Flash).

Pull-Up Network (PUN)

The complementary portion of a static CMOS logic gate constructed exclusively of pMOS transistors connected between $V_{DD}$ and the output node, responsible for driving the output to logic high when conducting.

Pull-Down Network (PDN)

The portion of a static CMOS logic gate composed entirely of nMOS transistors connected between the output node and ground, responsible for pulling the output to logic low when active.

Switching Threshold ($V_M$)

The DC operating point on the voltage transfer characteristic (VTC) of a CMOS inverter where the input voltage exactly equals the output voltage ($V_{\text{in}} = V_{\text{out}}$).

Worst-Case Delay Input Pattern

The specific combination of input transitions that activates the longest resistive path through series transistors in a pull-up or pull-down network, dictating the maximum propagation delay ($t_{pLH}$ or $t_{pHL}$).

Fan-In

The number of inputs connected to a single logic gate; large fan-in introduces series stacks of transistors that degrade circuit delay quadratically in distributed $RC$ models.

Fan-Out

The number of downstream gate inputs driven by a single output node, which directly determines the external load capacitance ($C_L$) seen by the driving gate.

Fanout-of-4 (FO4) Delay

A technology-independent delay metric defined as the propagation delay of an inverter driving four identical copies of itself, commonly used to normalize and compare circuit timing performance across process nodes.

Elmore Delay Model

An analytical method for estimating propagation delay in distributed $RC$ tree networks by computing the sum of each resistance multiplied by the downstream capacitance associated with that node ($\tau = \sum R_i C_i$).

Pseudo-nMOS Logic

A ratioed logic style that replaces the entire pMOS pull-up network with a single permanently grounded pMOS load transistor, trading static power dissipation for lower input capacitance and reduced silicon area.

Setup Time ($t_{\text{setup}}$)

The minimum time duration for which data must remain stable and valid prior to the arrival of the triggering clock edge to ensure accurate sampling by a flip-flop or register.

Hold Time ($t_{\text{hold}}$)

The minimum time duration for which data must remain stable and unchanged after the triggering clock edge has occurred to prevent accidental data corruption.

Clock-to-Q Delay ($t_{c-q}$)

The propagation time required for an active clock transition to alter and stabilize the output ($Q$) of a sequential element.

SR Latch Forbidden State

The invalid input combination ($S = 1, R = 1$ in a NOR-based latch) that forces both complementary outputs low ($Q = 0, \bar{Q} = 0$), creating non-deterministic behavior or metastability when inputs transition back to zero simultaneously.

Master-Slave Flip-Flop

A sequential structure consisting of two cascaded latches clocked on opposite phases (one transparent during clock low and one transparent during clock high) to achieve true edge-triggered operation without race conditions.

Dynamic Power Dissipation

The power consumed by charging and discharging load and parasitic capacitances during switching, governed by the formula $P_{\text{dyn}} = \alpha C_L V_{DD}^2 f$, where $\alpha$ is the activity factor.

Static Power Dissipation

Power continuously lost in unswitched CMOS circuits due to subthreshold leakage, reverse-biased junction leakage, and gate-oxide tunneling currents.

Activity Factor ($\alpha$)

The probability that a circuit node undergoes an energy-consuming $0 \rightarrow 1$ transition within a given clock cycle.

Diffusion Capacitance ($C_{\text{diff}}$)

The parasitic depletion capacitance formed between the reverse-biased source/drain diffusion regions and the semiconductor substrate or well, scaling with junction area and perimeter.

Miller Effect in CMOS Inverters

The capacitive multiplication phenomenon where the gate-to-drain overlap capacitance ($C_{gd}$) bridging input and output is effectively doubled ($2 \times C_{gd}$) when the inverter switches between opposite rails.

Logical Effort ($g$)

A metric describing the relative current-sourcing/sinking capability of a logic gate compared to an inverter with identical input capacitance, defined by $g = \frac{C_{\text{in}}}{C_{\text{in,inv}}}$ for equal current.

Electrical Effort ($h$)

The ratio of the external load capacitance driven by a gate to its internal input capacitance ($h = \frac{C_{\text{out}}}{C_{\text{in}}}$), representing the effective fanout ratio.

Parasitic Delay ($p$)

The intrinsic delay of a logic gate when driving zero external load capacitance, caused entirely by its own internal diffusion and wiring capacitances.

Optimal Stage Effort ($f_{\text{opt}}$)

The effort per stage that minimizes total path delay across a multi-stage logic path, expressed as $f = F^{1/N} \approx 3.6$ to $4.0$ for static CMOS designs.

Path Logical Effort ($G$)

The total logical effort of an entire multistage path, calculated as the product of the individual stage logical efforts ($G = \prod g_i$).

Path Effort ($F$)

The overall effort of a logic path, determined by the product of path logical effort ($G$), path branching effort ($B$), and path electrical effort ($H$), giving $F = GBH$.

Pass-Transistor Logic (PTL)

A logic implementation style that feeds inputs directly into transistor source/drain nodes rather than gates, minimizing device count at the expense of signal degradation.

Threshold Voltage Drop ($V_{DD} - V_{tn}$)

The signal attenuation occurring when an nMOS pass transistor transmits a logic high ($V_{DD}$), which clamps the transmitted voltage to $V_{DD} - V_{tn}$ due to the body effect.

Transmission Gate (TG)

A parallel arrangement of an nMOS transistor and a pMOS transistor driven by complementary clock signals ($\text{CLK}$ and $\overline{\text{CLK}}$) that conducts full rail-to-rail signals ($0\,\text{V}$ to $V_{DD}$) without a threshold drop.

Charge Sharing

An unintended voltage disturbance that occurs when charge stored on a dynamic node is redistributed among internal junction capacitances when intervening transistors switch on.

Precharge Phase

The operating phase of dynamic logic where the clock signal is low ($\text{CLK} = 0$), turning on a pMOS pull-up device to charge the dynamic output node unconditionally to $V_{DD}$.

Evaluation Phase

The operating phase of dynamic logic where the clock transitions to high ($\text{CLK} = 1$), enabling an nMOS evaluation foot transistor to conditionally discharge the dynamic node to ground according to input values.

Domino CMOS Logic

A dynamic circuit technique featuring a static CMOS inverter at the dynamic node output to ensure monotonic low-to-high transitions during the evaluation phase, preventing incorrect premature discharging in subsequent dynamic stages.

Monotonicity Requirement

The operational rule for dynamic logic stipulating that inputs to an nMOS evaluation network may transition at most once from low to high ($0 \rightarrow 1$) during evaluation and must never transition from high to low ($1 \rightarrow 0$).

6T SRAM Cell

A static memory cell comprising two cross-coupled inverters for bi-stable bit retention and two nMOS access transistors controlled by a wordline ($\text{WL}$) to interface with complementary bitlines ($\text{BL}$ and $\overline{\text{BL}}$).

SRAM Read Stability Ratio

The transistor sizing ratio constraint requiring the pull-down nMOS transistors to be stronger than the access nMOS transistors ($\frac{W_{PD}}{L_{PD}} > \frac{W_{AX}}{L_{AX}}$) so that internal nodes do not rise above $V_M$ and flip during a read.

SRAM Writeability Ratio

The transistor sizing ratio constraint requiring the access nMOS transistors to be stronger than the pull-up pMOS transistors ($\frac{W_{AX}}{L_{AX}} > \frac{W_{PU}}{L_{PU}}$) so incoming bitline signals can overpower the cross-coupled inverters to alter the stored state.

1T1C DRAM Cell

A dynamic memory storage element consisting of a single access transistor and a storage capacitor, requiring continuous periodic refresh cycles because charge bleeds off via subthreshold and reverse junction leakage.

Sense Amplifier

A high-sensitivity differential amplifier used in memory architectures to detect minute voltage deltas ($\Delta V$) developed across bitline pairs during a read operation and rapidly amplify them to full CMOS logic levels.

Floating-Gate Transistor

A specialized MOSFET containing an electrically isolated polysilicon gate embedded between the control gate and the channel, used in non-volatile memories (Flash/EEPROM) to store charge and shift the threshold voltage.

Fowler-Nordheim Tunneling

The quantum-mechanical transport mechanism used to program or erase floating-gate non-volatile memory cells by applying a high electric field across a thin oxide barrier to transfer electrons into or out of the floating gate.