Digital Integrated Circuits: CMOS Logic, Delay Optimization, Sequential Elements, and Semiconductor Memories

Static CMOS Logic Design and Transistor Sizing

• Fundamental Complementary Structure:

  • Static CMOS gates consist of two complementary sub-networks: a Pull-Up Network (PUN) constructed from PMOS transistors connected to $V_{DD}$, and a Pull-Down Network (PDN) constructed from NMOS transistors connected to $GND$.

  • The PUN and PDN are mutually exclusive during steady-state operation; when the PUN conducts, the output node charges to $V_{DD}$ (logic $1$), and when the PDN conducts, the output discharges to $GND$ (logic $0$).

  • Dual network topology: Inputs that place NMOS transistors in series within the PDN correspond to PMOS transistors in parallel within the PUN (e.g., NAND gates). Conversely, parallel NMOS configurations in the PDN map to series PMOS configurations in the PUN (e.g., NOR gates).

• Carrier Mobility and Inverter Sizing:

  • Electron mobility ($\mu_n$) in the NMOS channel is significantly higher than hole mobility ($\mu_p$) in the PMOS channel, typically by a factor of $\mu_n / \mu_p \approx 2$ to $3$.

  • To achieve symmetric rise ($t_r$) and fall ($t_f$) propagation delays and place the gate switching threshold ($V_M$) at approximately $V_{DD} / 2$, the PMOS channel width must be scaled larger than the NMOS channel width:         $\frac{W_p}{W_n} = \frac{\mu_n}{\mu_p} \approx 2 \text{ to } 3$

  • If a reference symmetrical unit inverter has an NMOS width of $W_n = 1\,W$ and a PMOS width of $W_p = 2\,W$ or $3\,W$, its total input capacitance equals:         $C_{in} = C_{g,n} + C_{g,p} = (1 + 2)\,C_g = 3\,C_g \quad (\text{or } 4\,C_g)$

• Transistor Sizing in Complex Gates:

  • N-input NAND Gate:

    • The PDN consists of $N$ NMOS transistors in series. To maintain an equivalent pull-down resistance $R_n$ equal to a unit inverter, each series NMOS must have its width scaled by $N$:             $W_{n,NAND} = N \times W_n$

    • The PUN consists of $N$ PMOS transistors in parallel. In the worst-case scenario where only one PMOS is conducting, its width must match the unit PMOS inverter width:             $W_{p,NAND} = W_p$

  • N-input NOR Gate:

    • The PDN consists of $N$ NMOS transistors in parallel. In the worst-case single-transistor conduction, the NMOS width is identical to a unit inverter:             $W_{n,NOR} = W_n$

    • The PUN consists of $N$ PMOS transistors in series. To maintain equivalent pull-up resistance $R_p$, each series PMOS must be scaled by $N$:             $W_{p,NOR} = N \times W_p = N \times 2\,W_n \quad (\text{or } N \times 3\,W_n)$

    • Because series PMOS sizing causes prohibitive area and parasitic capacitance penalties, high fan-in static NOR gates are avoided in high-performance digital libraries.

• Switching Point Characteristics:

  • The switching threshold ($V_M$) is defined as the operating point where $V_{in} = V_{out}$.

  • Deviations in the width ratio $\beta = (k_p / k_n)$ shift $V_M$:         $V_M = \frac{V_{th,n} + \sqrt{\frac{k_p}{k_n}} (V_{DD} - |V_{th,p}|)}{1 + \sqrt{\frac{k_p}{k_n}}}$

  • Increasing PMOS width shifts the transfer curve to the right (higher $V_M$), enhancing low noise margin ($NM_L$) at the expense of high noise margin ($NM_H$).

Elmore Delay Model and Parasitic RC Analysis

• Equivalent Resistance of MOSFET Channels:

  • In digital switching, transistors operate over saturation and triode regions. The channel is approximated by an effective switched-on resistance:         $R_{on} = \frac{1}{\mu C_{ox} \frac{W}{L} (V_{DD} - V_{th})}$

  • The effective channel resistance scales inversely with width: doubling $W$ halves the on-resistance $R$.

• Lumped and Distributed RC Delay:

  • For a uniform distributed RC transmission line representing long metal interconnect or polysilicon gates with total resistance $R_{total}$ and total capacitance $C_{total}$, the propagation delay calculated through diffusion modeling yields:         $\tau = \frac{1}{2} R_{total} C_{total}$

  • The factor of $1/2$ distinguishes a distributed network from a single lumped RC network where $\tau = R C$.

• Elmore Delay Formulation:

  • For an RC tree with non-cyclic topologies, the Elmore delay from the driving source to any destination leaf node $i$ is:         $\tau_{Di} = \sum_{k} R_{ik} C_k$

  • $R_{ik}$ is the path resistance from the input source to the common ancestor node shared between node $i$ and node $k$.

  • $C_k$ is the lumped capacitance located at node $k$.

• Internal Node Parasitics and Stacking Effects:

  • In a series stack of $N$ NMOS transistors discharging an output node to ground:

    • Each internal source/drain junction contains parasitic diffusion capacitance consisting of bottom-plate area capacitance ($C_j$) and sidewall perimeter capacitance ($C_{jsw}$):             $C_{diff} = C_{j} \cdot \text{Area} + C_{jsw} \cdot \text{Perimeter}$

    • The discharge delay involves charging/discharging all intermediate internal node capacitances through successive channel resistances, producing a delay that scales quadratically with stack depth $N$:             $\tau_{stack} \approx \sum_{k=1}^{N} (k \cdot R_{unit}) C_{internal} \propto N^2$

    • To mitigate stack delays, shared diffusion contacts and tailored transistor sizing (tapering transistors closer to ground to be larger) are implemented in critical paths.

Dynamic Power, Short-Circuit Power, and Leakage Mechanisms

• Dynamic Capacitive Power Dissipation:

  • During a $0 \rightarrow 1$ transition, an energy of $E_{VDD} = C_L V_{DD}^2$ is drawn from the power supply. Half of this energy ($\frac{1}{2} C_L V_{DD}^2$) is dissipated as heat in the PUN, and the remaining half is stored on the load capacitor $C_L$.

  • During the subsequent $1 \rightarrow 0$ transition, the stored energy ($\frac{1}{2} C_L V_{DD}^2$) is discharged to ground through the PDN and dissipated as heat.

  • Total dynamic switching power over continuous operation at clock frequency $f_{clk}$ with switching activity factor $\alpha$ is:         $P_{dyn} = \alpha C_L V_{DD}^2 f_{clk}$

• Short-Circuit Power Dissipation:

  • During input transitions with finite rise and fall times ($t_r, t_f$), there is an interval when the input voltage satisfies:         $V_{th,n} < V_{in} < V_{DD} - |V_{th,p}|$

  • In this window, both NMOS and PMOS conduct simultaneously, creating a direct current path from $V_{DD}$ to ground.

  • Short-circuit power is given by:         $P_{sc} = I_{peak} \cdot t_{sc} \cdot V_{DD} \cdot f_{clk}$

  • Minimizing input transition times relative to output transition times suppresses short-circuit current.

• Static Leakage Current Mechanisms:

  • Subthreshold Leakage ($I_{sub}$): Conduction in the weak inversion region when $V_{GS} < V_{th}$:         $I_{sub} = I_0 \exp\left( \frac{V_{GS} - V_{th}}{n (k_B T / q)} \right) \left( 1 - \exp\left( -\frac{V_{DS}}{k_B T / q} \right) \right)$

  • Gate-Oxide Tunneling Leakage ($I_{gate}$): Quantum mechanical tunneling of electrons/holes through thin gate dielectrics ($< 2\,nm$), highly dependent on electric field across the oxide ($E_{ox}$).

  • Junction Reverse-Bias Leakage ($I_{junc}$): Band-to-band tunneling (BTBT) and drift-diffusion current across the reverse-biased source/drain-to-substrate pn junctions.

Sequential Circuits, Latches, and Clock Timing Metrics

• Bistability and Cross-Coupled Inverter Pairs:

  • Two cross-coupled inverters form a static bistable storage element featuring two stable operating points ($Q=0, \bar{Q}=1$ and $Q=1, \bar{Q}=0$) and one metastable equilibrium point situated where the transfer curves intersect near $V_{M}$.

  • Metastability occurs when electrical noise or asynchronous switching places the differential node voltages exactly on the unstable threshold, leading to non-deterministic settling times governed by the loop regeneration time constant ($\tau_{regen} = R_{eq} C_{node}$).

• SR Latch Architectures and Operation:

  • NOR-based SR Latch:

    • Active-high inputs $S$ (Set) and $R$ (Reset).

    • Input condition $S=1, R=0$ forces $Q=1, \bar{Q}=0$.

    • Input condition $S=0, R=1$ forces $Q=0, \bar{Q}=1$.

    • Input condition $S=0, R=0$ corresponds to the hold (quiescent) state.

    • Input condition $S=1, R=1$ is forbidden; both outputs are forced to $0$, violating complementarity ($Q = \bar{Q} = 0$), and leading to race conditions/metastability upon simultaneous transitions back to $S=0, R=0$.

  • NAND-based $\bar{S}\bar{R}$ Latch:

    • Active-low control inputs $\bar{S}$ and $\bar{R}$.

    • Quiescent state occurs when $\bar{S}=1, \bar{R}=1$.

    • $\bar{S}=0, \bar{R}=1$ sets $Q=1$, while $\bar{S}=1, \bar{R}=0$ resets $Q=0$.

    • Forbidden input combination is $\bar{S}=0, \bar{R}=0$.

• Master-Slave D Flip-Flop Configuration:

  • Constructed by cascading two level-sensitive D-latches in series: a Master latch followed by a Slave latch, driven by complementary clock signals ($CLK$ and $\overline{CLK}$).

  • When $CLK=0$ ($\overline{CLK}=1$):

    • Master latch is transparent; it samples the external input $D$ onto intermediate node $Q_M$.

    • Slave latch is opaque (in hold state); it isolates the primary output $Q$ from variations at $Q_M$.

  • When $CLK$ transitions from $0 \rightarrow 1$:

    • Master latch becomes opaque, capturing the logic level present at $D$ immediately before the clock edge.

    • Slave latch becomes transparent, propagating the captured state from $Q_M$ to the system output $Q$.

  • This arrangement prevents through-transparency and implements edge-triggered sequential behavior.

• Critical Sequential Timing Parameters:

  • Setup Time ($t_{setup}$): The minimum continuous duration that data input $D$ must remain stable before the active clock edge occurs to ensure valid latching.

  • Hold Time ($t_{hold}$): The minimum continuous duration that data input $D$ must remain stable after the active clock edge occurs to prevent overwriting the sampled data.

  • Clock-to-Q Propagation Delay ($t_{clk-q}$): The elapsed time between the arrival of the active clock edge and the valid transition of the output $Q$.

  • Maximum Operating Frequency Constraint:         $T_{clk} \ge t_{clk-q} + t_{comb,max} + t_{setup}$         $f_{max} = \frac{1}{T_{clk,min}} = \frac{1}{t_{clk-q} + t_{comb,max} + t_{setup}}$

  • Hold Time Violation Condition:         $t_{clk-q} + t_{comb,min} \ge t_{hold} + t_{skew}$

    • If the minimum logic delay is too small, an early arriving data signal can race through the logic and corrupt the subsequent register on the same clock cycle.

Method of Logical Effort and Delay Optimization

• Linear Delay Model:

  • Normalized delay $d$ of a logic gate driving a load is expressed as:         $d = f + p = g \cdot h + p$

  • $g$ is the Logical Effort, representing the gate's topological efficiency at delivering current relative to an inverter having identical input capacitance.

  • $h$ is the Electrical Effort (effective fan-out):         $h = \frac{C_{out}}{C_{in}}$

  • $p$ is the Parasitic Delay, representing intrinsic internal diffusion delay when driving zero external load ($C_{out} = 0$).

• Logical Effort Values for Standard Topologies:

  • Inverter: $g = 1$, $p_{inv} = 1$

  • N-input NAND Gate:         $g_{NAND} = \frac{N + \frac{\mu_n}{\mu_p}}{1 + \frac{\mu_n}{\mu_p}} = \frac{N + 2}{3} \quad (\text{for } \mu_n/\mu_p = 2)$

    • 2-input NAND: $g = 4/3$, $p = 2$

    • 3-input NAND: $g = 5/3$, $p = 3$

  • N-input NOR Gate:         $g_{NOR} = \frac{1 + N \cdot \frac{\mu_n}{\mu_p}}{1 + \frac{\mu_n}{\mu_p}} = \frac{1 + 2\,N}{3} \quad (\text{for } \mu_n/\mu_p = 2)$

    • 2-input NOR: $g = 5/3$, $p = 2$

    • 3-input NOR: $g = 7/3$, $p = 3$

• Path Delay Minimization in Multi-Stage Inverter Chains:

  • For a path of $N$ stages driving a capacitive load $C_L$ from an input capacitance $C_{in}$:

    • Path Logical Effort: $G = \prod_{i=1}^{N} g_i$

    • Path Electrical Effort: $H = \frac{C_L}{C_{in,1}}$

    • Path Branching Effort: $B = \prod_{i=1}^{N} b_i$, where $b_i = \frac{C_{on-path} + C_{off-path}}{C_{on-path}}$

    • Total Path Effort: $F = G \cdot B \cdot H$

  • Minimum path delay occurs when the stage effort is equal across all stages:         $\hat{f} = g_i h_i = F^{1/N} = \sqrt[N]{F}$

  • The minimum total path delay is:         $D_{min} = N \cdot F^{1/N} + \sum_{i=1}^{N} p_i = N \cdot \hat{f} + P$

  • Optimal Number of Stages ($N_{opt}$):

    • Differentiating path delay with respect to $N$ yields the condition:             $\hat{f} \ln(\hat{f}) - \hat{f} + p_{inv} = 0$

    • For ideal parasitic delay $p_{inv} = 0$, $\hat{f} = e \approx 2.718$.

    • For realistic CMOS inverters ($p_{inv} \approx 1.0$), optimal stage effort is $\hat{f} \approx 3.6$ to $4.0$.

    • Optimal stage count is determined by:             $N_{opt} \approx \frac{\ln(F)}{\ln(3.6)}$

• Inverter Sizing Procedure:

  • Given stage effort $\hat{f} = 4$, input capacitance for stage $i$ is sized according to:         $C_{in,i} = \frac{g_i \cdot C_{out,i}}{\hat{f}} = \frac{C_{in,i+1}}{\hat{f}}$

  • Working backward from the final external load $C_L$, each buffer transistor width scales upward geometrically by a factor of $\approx 3.6$ to $4$.

Pass-Transistor Logic and Complementary Transmission Gates

• Single-MOSFET Pass-Transistor Limitations:

  • NMOS Pass Transistor:

    • Transfers a logic $0$ ($0\,V$) completely to the output (strong $0$) because $V_{GS} = V_{DD}$, keeping the device in linear/triode conduction until $V_{out} = 0\,V$.

    • Transfers a degraded logic $1$ (weak $1$): as the output charges up, the gate-to-source voltage drops to $V_{GS} = V_{DD} - V_{out}$. Conduction stops when $V_{GS} = V_{th,n}$, causing the output to clamp at:             $V_{out,max} = V_{DD} - V_{th,n}$

  • PMOS Pass Transistor:

    • Transfers a full rail-to-rail logic $1$ ($V_{DD}$) completely (strong $1$).

    • Transfers a degraded logic $0$ (weak $0$): conduction ceases when the source drops to $|V_{th,p}|$, clamping the output at:             $V_{out,min} = |V_{th,p}|$

• Body Effect in Pass Transistors:

  • Because the substrate of an NMOS pass transistor is permanently connected to $GND$ while its source node rises toward $V_{DD} - V_{th,n}$, a significant source-to-body reverse bias voltage ($V_{SB} > 0$) develops.

  • The threshold voltage increases according to the body effect equation:         $V_{th,n} = V_{th0} + \gamma \left( \sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F} \right)$

  • This dynamic threshold elevation drops the transferred high voltage significantly below nominal levels (e.g., dropping a $1.8\,V$ supply down to $1.1\,V$–$1.2\,V$).

  • When driving a subsequent static CMOS inverter, this attenuated voltage causes static DC current in the receiver because the PMOS pull-up cannot turn off completely ($V_{GS,p} = V_{out} - V_{DD} \ne 0$).

• Complementary Transmission Gate (TG):

  • Constructed by placing an NMOS and a PMOS transistor in parallel, gated by complementary control signals ($C$ and $\bar{C}$).

  • When active ($C=1, \bar{C}=0$):

    • For low input voltages ($0 \le V_{in} < |V_{th,p}|$), the NMOS operates in saturation/triode mode and passes a solid ground.

    • For high input voltages ($V_{DD} - V_{th,n} < V_{in} \le V_{DD}$), the PMOS conducts and pulls the output up to $V_{DD}$.

    • In intermediate ranges, both devices conduct simultaneously.

  • The combined equivalent resistance is uniform across the entire voltage range:         $R_{TG} = R_{on,n} \parallel R_{on,p} \approx \text{constant}$

  • Provides full rail-to-rail dynamic voltage swings ($0\,V$ to $V_{DD}$).

• Multiplexer (MUX) Implementation:

  • A 2-to-1 multiplexer using transmission gates requires two TGs controlled by selection signals $S$ and $\bar{S}$, joined at a common output node followed by a restorer inverter.

  • This design uses only 6 transistors (including the control inverter), compared to 12 transistors required in static CMOS AND-OR-INVERT configurations, reducing input load and silicon area.

Dynamic CMOS Logic and Domino Circuits

• Precharge-Evaluate Logic Mechanism:

  • Dynamic gates employ a single clock signal ($\phi$) to cycle between two distinct functional phases, eliminating the static PMOS logic network:

    • Precharge Phase ($\phi = 0$):

      • A pull-up PMOS turns ON, precharging the dynamic output node to $V_{DD}$.

      • An evaluation NMOS in series with the PDN is held OFF, preventing static paths to ground.

    • Evaluate Phase ($\phi = 1$):

      • The precharge PMOS turns OFF, and the evaluation footer NMOS turns ON.

      • If the logic inputs satisfy the pull-down conditions, the dynamic node discharges to $GND$.

      • If the logic inputs do not satisfy the conditions, the dynamic node floats high on its lumped capacitance ($C_L$).

• Vulnerabilities of Dynamic Nodes:

  • Charge Leakage: Subthreshold and reverse-biased junction leakage currents continuously drain charge from a floating dynamic high node during extended evaluation phases, establishing a strict lower bound on clock frequency ($f_{clk,min}$).

  • Charge Sharing: When the dynamic node is precharged high and internal node capacitances within the PDN are discharged, turning ON an upper transistor without discharging the entire path redistributes charge, causing an unintended voltage drop:         $\Delta V_{out} = V_{DD} \left( \frac{C_{int}}{C_{L} + C_{int}} \right)$

    • If $\Delta V_{out} > V_{th,n}$, downstream gates trigger false transitions.

  • Keeper Circuits: A small "keeper" PMOS connected across the precharge node, controlled by the inverted output, supplies compensation current to counteract subthreshold leakage and stabilize the floating node without degrading evaluate speed.

• Domino Logic Cascading Constraint:

  • Direct cascading of dynamic gates leads to race conditions. If an upstream dynamic gate's output is precharged to $1$, it prematurely turns ON the evaluate transistor of the downstream dynamic gate when $\phi \rightarrow 1$, potentially discharging the downstream node before the upstream gate evaluates.

  • The Domino Rule: Every dynamic gate must be followed by a static CMOS inverter. During precharge, the dynamic node is $1$, so the inverter output is $0$. Downstream evaluation NMOS transistors remain OFF during precharge and can only switch monotonically ($0 \rightarrow 1$) during evaluation.

Semiconductor Memory Architectures and Decoding

• Hierarchical Memory Organization:

  • A random-access memory array containing $2^K$ words of $M$ bits each ($2^K \times M$ bits) is organized as a 2D matrix of storage cells.

  • The memory structure consists of:

    • An address bus partitioned into row addresses ($K_{row}$ bits) and column addresses ($K_{col}$ bits), where $K = K_{row} + K_{col}$.

    • Row Decoder: A $K_{row}$-to-$2^{K_{row}}$ decoder asserting exactly one horizontal Wordline ($WL$) at a time.

    • Column Decoder: Selects a subset of vertical Bitlines ($BL, \overline{BL}$) via pass gates/multiplexers to route to the input/output sense circuitry.

    • Sense Amplifiers: Differential amplifiers detecting small voltage differentials ($\Delta V \approx 100\,mV$–$200\,mV$) between bitlines, accelerating access times.

• Row Decoders and Wordline Driving:

  • Implements wide NOR or NAND logic. In high-density memories, dynamic or pseudo-NMOS NOR decoders are preferred over static gates to minimize transistor counts on pitched wordline boundaries.

  • A predecoded structure partitions the primary address decoding into smaller subsets (e.g., 2-to-4 predecoders), driving final row-select driver stages to minimize total gate loading.

Static and Dynamic RAM: 6T SRAM and 1T-1C DRAM Cell Operation

• Six-Transistor (6T) SRAM Cell Architecture:

  • Consists of two cross-coupled CMOS inverters ($M_1/M_2$ and $M_3/M_4$) forming the bistable latch, accessed by two NMOS pass transistors ($M_5$ and $M_6$) connected to complementary bitlines ($BL$ and $\overline{BL}$).

  • Gates of $M_5$ and $M_6$ are controlled by the horizontal wordline ($WL$).

• SRAM Read Operation and Sizing Constraint (Cell Ratio):

  • Read Sequence:

    1. Bitlines ($BL$ and $\overline{BL}$) are precharged to $V_{DD}$ and then floated.

    2. Wordline is driven high ($WL = V_{DD}$), turning ON access transistors $M_5$ and $M_6$.

    3. Assuming cell stores $Q=0$ and $\bar{Q}=1$, current flows from $BL$ through $M_5$ and driver NMOS $M_1$ to ground, discharging $BL$.

    4. Intermediate node $Q$ rises to an intermediate voltage $V_{read}$ determined by the voltage divider between $M_5$ and $M_1$:             $V_{read} = \frac{R_{on,M1}}{R_{on,M1} + R_{on,M5}} V_{DD}$

  • Read Stability Constraint: To prevent accidental flipping of the cross-coupled cell, $V_{read}$ must not exceed the switching threshold of inverter $M_3/M_4$ ($V_{th,n}$):         $V_{read} < V_{th,n}$

  • Cell Ratio ($CR$): The transconductance/width of the pull-down driver transistor must be larger than that of the access transistor:         $CR = \frac{(W/L)_{driver}}{(W/L)_{access}} = \frac{(W/L)_1}{(W/L)_5} \ge 1.2 \text{ to } 1.5$

• SRAM Write Operation and Sizing Constraint (Pull-up Ratio):

  • Write Sequence:

    1. Column drivers force one bitline to ground ($BL = 0$) and the other to $V_{DD}$ ($\overline{BL} = V_{DD}$).

    2. Wordline is asserted ($WL = V_{DD}$).

    3. The low bitline discharges the high storage node ($\bar{Q}=1 \rightarrow 0$) through access transistor $M_6$, overcoming the pull-up PMOS $M_4$.

  • Writeability Constraint: Access transistor $M_6$ must be strong enough to pull node $\bar{Q}$ down below the threshold needed to turn on inverter $M_1/M_2$ against pull-up PMOS $M_4$.

  • Pull-up Ratio ($PR$):         $PR = \frac{(W/L)_{pull-up}}{(W/L)_{access}} = \frac{(W/L)_4}{(W/L)_6} \le 0.5 \text{ to } 0.8$

  • Combined sizing hierarchy: $(W/L)_{driver} > (W/L)_{access} > (W/L)_{pull-up}$.

• One-Transistor One-Capacitor (1T-1C) DRAM Operation:

  • The storage cell consists of a single NMOS access transistor and an explicit trench/stacked storage capacitor ($C_s \approx 25\,fF$–$40\,fF$).

  • Read Operation and Charge Sharing:

    • Bitline with large parasitic capacitance ($C_{BL} \approx 100\,fF$–$300\,fF$) is precharged to $V_{DD} / 2$.

    • Asserting $WL$ connects $C_s$ to $C_{BL}$, causing charge redistribution. The resulting bitline voltage shift is:             $\Delta V_{BL} = \frac{C_s}{C_s + C_{BL}} \left( V_s - \frac{V_{DD}}{2} \right)$

    • Because $C_{BL} \gg C_s$, the signal is small ($\Delta V_{BL} \approx 100\,mV$–$200\,mV$), requiring high-gain differential cross-coupled sense amplifiers.

  • Destructive Read and Refresh: Reading discharges $C_s$. Sense amplifiers must restore the rail-to-rail voltage back into the cell immediately after sensing. Continuous leakage through the access transistor requires periodic refresh cycles (typically every $64\,ms$).

Non-Volatile Semiconductor Memories: ROM and Flash Technologies

• Read-Only Memory (ROM) Arrays:

  • NOR ROM Array:

    • Bitlines are precharged to $V_{DD}$.

    • Each memory cell consists of an NMOS transistor whose gate connects to a Wordline ($WL$) and whose drain connects to a Bitline ($BL$).

    • Programming a logic $0$ consists of placing an active NMOS at the intersection; when the corresponding $WL$ goes high, the NMOS discharges the bitline.

    • Programming a logic $1$ consists of omitting the transistor (or omitting the diffusion/contact contact), leaving the bitline pulled high.

    • Characterized by high access speeds, but larger footprint due to parallel bitline connections.

  • NAND ROM Array:

    • NMOS transistors are connected in series along a vertical bitline.

    • In unprogrammed cells (logic $0$), a functional transistor is present. In programmed cells (logic $1$), the transistor channel is continuously shorted via a threshold implant or diffusion bypass.

    • To read a cell, its selected wordline is driven to $0\,V$, while all unselected series wordlines are driven high to act as pass transistors.

    • Provides significantly higher packing density than NOR ROM, at the cost of higher series resistance and lower read speeds.

• Floating-Gate MOSFET and Threshold Programming:

  • Floating-gate transistors contain an electrically isolated polysilicon gate embedded between the channel oxide and a control gate.

  • Trapping electrons on the floating gate shifts the effective threshold voltage ($V_{th}$) observed from the control gate:         $\Delta V_{th} = -\frac{Q_{FG}}{C_{OX,top}}$

  • Unprogrammed/Erased State: Zero or net positive charge on the floating gate yields a low threshold ($V_{th,low}$). Applying normal read voltage on the control gate turns the device ON.

  • Programmed State: Stored negative charge raises the threshold to $V_{th,high}$. The normal read voltage cannot turn the device ON, representing a programmed logic state.

• Programming and Erase Mechanisms:

  • Channel Hot-Electron (CHE) Injection: High $V_{DS}$ accelerates electrons along the channel; high control gate voltage ($V_{GS}$) bends the dielectric band structure, injecting hot electrons across the $Si/SiO_2$ potential barrier onto the floating gate.

  • Fowler-Nordheim (FN) Tunneling: A high electric field ($> 10\,MV/cm$) across a thin tunneling oxide induces quantum tunneling through the triangular barrier, enabling bidirectional movement of electrons for bulk erase and programming.

• Flash Architectures: NOR vs. NAND Flash:

  • NOR Flash:

    • Cells are connected in parallel to bitlines, allowing fast, random access to individual bytes.

    • Ideal for execute-in-place (XIP) code execution in microcontrollers and firmware storage.

  • NAND Flash:

    • Cells are placed in series strings (typically 32 to 128 transistors) bounded by block-select transistors.

    • Eliminates individual cell contacts, maximizing silicon storage density per unit area.

    • Read and write operations occur in pages (e.g., $4\,KB$–$16\,KB$), while erase operations occur in entire blocks (e.g., hundreds of pages), making it suitable for mass data storage (SSDs, USB media).