Digital Electronics Practice Flashcards

Flashcards covering digital electronics concepts including logic families (TTL/CMOS), RC circuit behavior, timing analysis, and communication protocols based on lecture exam practice exam solutions.

Low-pass RC Filter (output on capacitor)

A circuit configuration where, if state durations are much longer than the time constant $\tau = RC$, the peak-to-peak output amplitude is approximately equal to the input and the mean output voltage equals the mean input voltage.

Digital Signal Parameters

Discrete voltage levels that represent logic states (0 and 1), distinguishing them from physical circuit parameters like propagation times, resistance, or capacitance.

Logic Level Condition (HIGH)

The requirement that the minimum guaranteed output voltage $V_{OH1}$ must be greater than the minimum accepted input voltage $V_{IH2}$ for a HIGH logic state to be correctly recognized.

PWM (Pulse Width Modulation)

A digital signal that encodes information in the duty cycle rather than amplitude, allowing transmission via standards like RS-232 and minimizing power dissipation by operating transistors in switching mode.

Bipolar Transistor Minimum Power Dissipation

Occurs when the transistor is saturated because the collector-emitter voltage $V_{CE(sat)}$ is very low (approx. $0.2\,V$), resulting in a low product of voltage and current ($P \approx V_{CE} \cdot I_{C}$).

74LS (Low Power Schottky)

A logic family that uses Schottky diodes to prevent deep saturation for increased speed while consuming less power than standard TTL.

Standard TTL Power Supply

Requires a fixed continuous voltage of $5\,V$, typically within a tolerance range of $4.75\,V$ to $5.25\,V$ ($\pm 5\%$).

CMOS Input Impedance

A massive impedance provided by the oxide-isolated gates of MOSFET transistors, resulting in negligible static input currents (picoamperes or nanoamperes).

Tri-State (3-State) Logic

Logic gates that include an Enable input to allow for three output states: HIGH, LOW, or High Impedance (Hi-Z), facilitating the connection of multiple outputs to a common bus.

Wired-AND

A logic structure realized by connecting open-collector or open-drain outputs in parallel to a single pull-up resistor; the bus remains HIGH only if all outputs are OFF.

Fan-out

The number of digital inputs that a single output can drive simultaneously; increasing it adds capacitive load and reduces switching speed.

Astabil Multivibrator

A circuit that automatically and continuously switches between two logic states (HIGH and LOW), acting as a clock generator or oscillator.

Pipelining Throughput

An advantage of pipeline implementation in sequential circuits where multiple data streams are processed concurrently, significantly increasing the result rate per unit of time.

UART (Universal Asynchronous Receiver Transmitter)

A sequential digital circuit that communicates data asynchronously using internal shift registers and a local clock, commonly implemented in FPGA logic.

I2C Bus Voltage Range

In a system with a $3\,V$ supply, the voltage on I2C lines (SDA, SCL) swings between approximately $0\,V$ (active LOW) and $3\,V$ (the pull-up level).

Push-Pull Output Stage

An output configuration using two active transistors to pull the signal both HIGH and LOW, providing faster rise times compared to a passive pull-up resistor.

CMOS Dynamic Power Consumption

The primary power consumption in CMOS circuits, calculated as $P = f \cdot C \cdot V_{DD}^2$, showing it increases with frequency, load capacitance, and supply voltage.

Transmission Gate (Analog Switch)

A bidirectional CMOS structure that acts like an electronic switch, passing a wide range of analog signal levels from $0\,V$ to $V_{DD}$ without logic interpretation zones.

Pipelining Latency

A disadvantage of pipeline implementation where the total time required for a single instruction to complete (latency) increases due to the introduction of intermediate registers.

Miniaturization Noise Margin Penalty

A disadvantage of physical scaling in CMOS where lower supply voltages required for thinner oxides result in reduced absolute distance between HIGH and LOW thresholds.

Monostabil Multivibrator

A circuit that generates a single pulse of a precise duration when triggered, moving from a stable state to a quasi-stable state and back.

SRAM (Static Random Access Memory)

A type of volatile memory that uses cross-interconnected bistable structures to store data as long as power is maintained.

High-pass RC Filter (output on resistor)

A circuit configuration that blocks DC (direct current), resulting in a mean output voltage of approximately zero regardless of the input's DC component.

Static Timing Analysis (Setup Condition)

A timing requirement for sequential circuits where the clock period $T$ must be greater than or equal to the sum of the source register propagation time $t_{CQ}$, combinatorial logic delay $t_{p}$, and destination register setup time $t_{s}$ ($T \geq t_{CQ} + t_{p} + t_{s}$).