Computer Organization-Chapter 2

3 major parts of a computer system

CPU, memory, I/O devices

CPU 3 main functions

fetch, decode, execute

Parts of the CPU

Control Unit-fetches and decodes instructions

ALU-executes instructions

Memory-registers which hold data to be operated on

what are all CPU components connected by

buses

bus

collection of wires which carry multiple signals functioning together

3 types of processors

general purpose, single purpose, application specific

instruction register

holds the instructions being executed

program counter

holds a pointer to the next instruction

Data path

Loop structure that carries out instruction in CPU

2 types of instructions

register-register

register-memory

7 Instruction Executions

1) fetch instruction

2) increment the program counter

3) decode type of instruction

4) if register-memory decode address

5) if the register-memory read data word

6) execute an instruction

7) goto step 1

To execute as many instructions per unit time as possible, what could we do

increase clock speed

execute instructions directly in hardware

easily decoded instructions

only loads and stores should reference memory

use as many registers as necessary

order instructions to minimize delays

CISC

complex instructions created to make computers more powerful and backward compatible

RISC

a system with relatively few instructions that are executed directly by hardware

Superscalar Architecture

multiple pipelines

VLIW Architectures

statically optimize and encode several instructions at a time

Array Processors

identical processors performing the same instructions but on different data

Vector Processor

one heavily-pipelined ALU but load vectors in separate vector registers to perform the math

Multiple Processor Computers

multiple processors which share a common memory

Multicomputer

systems don't have shared memory but are in essence strand-alone systems connected by some sort of network

code

memory which is read but seldom written to

data

variables that the program uses

Von Neumann architecture

uses a single address and data bus to reference memory

Harvard Architecture

uses a seperate data and address bus for each

bit

basic unit of todays digital memory

byte

a group of 8 bits

nybble

a group of 4 bits

word

the basic unit of size of internal registers or how many bits wide the data bus is

cell

basic physical division of memory-smallest addressable size of memory

what does cell size determine

how much information is stored at each address

Big Endian

store most significant byte at most significant address

Little Endian

store least significant byte at most significant address

to modify single bits what to do

use bit masking, and bitwise operators

pointer

a variable which stores an address to data

most common use of pointers

allow a function to modify a variable passed to it

Dynamic memory

memory allocated at runtime, not compile time

error correcting codes

redundancy of parity bits can be used to enable error detection

Minimum hamming distance to correct a single bit error

3

cache

small and fast memory which holds only the most heavily used instructions

What is the unit in a CPU called which would perform an operation as addition or ORing

ALU

What register holds the address to the next instruction to be fetched

Program Counter

When comparing building to executing computer instructions. What is a tool belt analagous to

cache

The size of its registers is generally called its _____ size

word

which category of CPU would DSP processor fall into

Application Specific

difference between multi-processor computer and arrays computers

multiprocessor computers are computers that have multiple processors sharing the same memory. Array processors consist of identical processors performing the same instruction, on different data

Advantage of having a relatively large cell size

1) computer can access memory faster

2)computer can access more memory with fewer address lines

3) accessing integers is simpler

All else being equal which computer architecture should be faster?

Harvard