Microprocessor PreFinal

Temporal Aspects

The logic components are characterized temporally for a temperature range and a range of the supply voltages.

Peripheral Interfacing

When one or more devices are to be connected to a microprocessor, an interface network for each device is required.

Buffering

 It is necessary to take care of incompatibility between the microprocessor and the peripheral.

Address Decoding

It is required to select one of the several peripherals connected in the system.

Command Decoding

 It is required for peripherals that perform actions other than data transfers.

Timing and Control

All the above functions require timing and control.

Serial Communication Interface

In this type of communication, the interface gets a single byte of data from the microprocessor and sends it bit by bit to the other system serially and vice-a-versa.

Parallel Communication Interface

In this type of communication, the interface gets a byte of data from the microprocessor and sends it bit by bit to the other systems in simultaneous (or) parallel fashion and vice-a-versa.

Programmed Data Transfe

A software routine residing in memory requests the peripheral device for data transfer to or from the microprocessor. Generally, the data is transferred to or from the accumulator through some microprocessors; other internal registers may also participate in the transfer.

Direct Memory Access (DMA) Transfer or Cycle Stealing Transfer

 In this mode, the data transfer is controlled by the peripheral device. The microprocessor is forced to hold on by an I/O device until the data transfer between the device and the memory is complete.

Peripheral Logic

The term "glue logic" (sticky logic) is a generic term that designates a set of logical operators (General-Purpose). When a microprocessor integrates a storage unit (latch), it is said to be glueless in which there is no longer any need for this external logic since it is integrated.

Direct Memory Access

Designed to transfer data at the fastest rate. It allows the device to transfer the data directly to/from memory without any interference from the CPU. Using this controller, the device requests the CPU to hold its data, address, and control bus, so the device is free to transfer data directly to/from the memory.

Clock signal

A periodic logic signal that rates or synchronizes the operation of a circuit or a system.

Oscillator

Can be associated with electronics to generate all the signals of the subsets of the system.

T-state

Corresponds to a period of the internal clock which cadences the operation of the microprocessor unit. It can also be called a subdivision of an execution cycle.

Data flow

Performed the physical manipulation of the data values.

Control flow

Dynamically determined the sequence in which these manipulations were done.

Principle of orthogonal

Specifies that each instruction should perform a unique task without duplicating or overlapping the functionality of other instructions.

Instruction

A coded program step that tells the processor what to do for a single operation in a program.

Instruction cycle

The process of fetching and executing an instruction.

Single-cycle

Each instruction executes in a single clock cycle.

Multi-cycle

Each instruction is broken up into a series of short steps.

Pipelined

Each instruction is broken up into a series of steps.

Degree of parallelism of a processor

Number of operations it can execute concurrently.

Instruction-level parallelism

Exists when instructions in a (program) sequence are independent and thus can be executed in parallel by overlapping.

Machine parallelism

A measure of the ability of the processor to take advantage of instruction-level parallelism. It is determined by the number of instructions that can be fetched and executed at the same time and by the speed that the processor uses to find independent instructions.

Pipelining

An implementation technique in which multiple instructions are overlapped in execution.

Machine cycle

The time required between moving an instruction one step down the pipeline. The length of a machine cycle is determined by the time required for the slowest pipeline stage.

Base Pipeline

• Per cycle is issued one (1) instruction.

• Operations are broken down into sub-tasks.

• Different sub-tasks from different operations run in parallel.

Superpipeline

Machines can issue only one instruction per cycle, but they have cycle times shorter than the time required for any operation.

Superscalar Pipeline

• Degree n can issue n instructions per cycle.

• It multiplies the issued units. Multiple operations issued and completing simultaneously.

• Simple instruction latency measured in one (1) cycle. Per cycle is issued four (4) instructions.

• Example: n=4, m=4. (see Figure)

Pipeline Hazards

Requires that operation performed by a stage must not depend on the operation(s) performed by another stage(s). Dependencies are the property of programs.

Hazard

The situation that prevents the next instruction in the instruction stream from executing during its designated clock cycle.

Structural hazards (resource conflicts)

The hardware cannot support all possible combinations of instructions in simultaneous overlapped execution.

Starvation

It is the result of the conservative allocation of resources in which a single process is prevented from execution because it's kept waiting for resources that never become available.

Critical region

It is the part of the program that must complete execution before other processes can have to the resources being used.

Deadlock

A problem occurring when the resources needed by some processes to finish execution are held by other processes, in turn, are waiting for other resources to become available.

Control hazards (procedural conflicts)

Instructions following a conditional branch instruction have a procedural dependency on the conditional branch instructions.

Data hazards

Hazards arise when an instruction depends on the results of previous instruction in a way that is exposed by the overlapping of instructions in the pipeline.