FDE Cycle and CPU Components

Vocabulary terms covering CPU registers, LMC instructions, and the stages of the Fetch-Decode-Execute cycle.

Fetch Decode Execute

The cycle that describes the basic operation of a CPU, involving getting an instruction from memory, interpreting it, and carrying it out.

MAR

Memory address register; a component that stores the memory location of data or instructions currently being accessed.

MDR

Memory data register; a component used to hold the data or instruction that has just been fetched from or is about to be sent to memory.

CIR

Current instruction register; a component that holds the instruction that is Currently being decoded and executed.

Control unit

The component of the CPU that coordinates the activities of the cycle and decodes the instructions.

ALU

Arithmetic Logic Unit; the component where the CPU executes calculations and logical operations.

Buses

The communication pathways used to transfer data (data bus) and memory addresses (address bus) between the CPU and RAM.

Program counter

A register that keeps track of the address of the next instruction to be fetched.

Accumulator

A register used in the CPU to store the logic or arithmetic results during the Execute stage.

LMC

Little Man Computer; a simulator used to model computer architecture and the FDE cycle.

INP

An instruction in the LMC program that stands for Input.

HLT

An instruction in the LMC program that stands for Halt; it signals the end of the program.

num1

A label on lines $2$ and $4$ of the LMC 'Adding $2$ inputs' program representing a memory location.

Address bus

The bus along which the CPU sends a signal requesting an instruction from a specific numbered location in RAM.

Data bus

The bus used to transfer instructions or data from RAM back to the CPU.

Secondary memory

The storage from which instructions are initially loaded into RAM before the FDE cycle begins.

RAM

Random Access Memory; where instructions are stored in numbered memory locations to be fetched by the CPU.

Decode stage

The part of the cycle where the CPU interprets the instruction fetched from memory.

Execute stage

The part of the cycle where the CPU carries out the instruction, potentially fetching more data from memory or storing a result in RAM.