Computer Memory and Peripheral Devices Review

Vocabulary term flashcards covering Computer Memory, Peripheral Devices, Memory Hierarchy, Cache Mapping techniques, Virtual Memory, and I/O Data Transfer modes based on Unit-3 lecture transcripts.

Memory Hierarchy

A computer system design enhancement developed based on a program behavior known as locality of reference to organize memory and minimize access time.

Capacity

The global volume of information the memory can store, which increases as one moves from the top to the bottom of the memory hierarchy.

Access Time

The time interval between the read/write request and the availability of the data; it increases while moving from the top to the bottom of the hierarchy.

Cost Per Bit

A characteristic of memory hierarchy where the price of storage increases as one moves from the bottom to the top of the hierarchy.

Static RAM (SRAM)

A type of main memory consisting of internal flip-flops that store binary information valid as long as power is supplied, featuring shorter read and write cycles.

Dynamic RAM (DRAM)

A type of main memory that stores binary information in the form of electric charges applied to capacitors made available by metal oxide semiconductor (MOS) transistors.

Internal Memory

Also known as primary or main memory, it is attached inside the computer system, is not portable, and is directly accessible by the CPU.

ROM (Read Only Memory)

A type of non-volatile internal memory where data is written during manufacture and cannot be changed; if a single bit is wrongly input, it becomes useless.

External Memory

Also known as secondary memory, it stores data externally for permanent storage and is portable (e.g., hard disk drives, optical drives).

Cache Memory

A high-speed, small-sized memory used to synchronize with the high-speed CPU to improve performance by holding frequently used data for instant availability.

Level 1 Cache (L1)

The first level of cache memory, present inside the CPU, ranging in size from $2\,KB$ to $64\,KB$, and working at the same speed as the CPU.

Level 3 Cache (L3)

A cache located outside the CPU used to enhance performance of $L1$ and $L2$, with a memory size range from $1\,MB$ to $8\,MB$, faster than RAM but slower than $L2$.

Cache Hit

A condition occurring when the CPU finds the required data inside the cache memory.

Cache Miss

A condition occurring when the data sought by the CPU is not found within the cache memories.

Cache Mapping

A technique by which contents of main memory are brought into the cache memory, involving dividing main memory into blocks and cache into lines.

Direct Mapping

A technique where a particular block of main memory can map only to a specific line of the cache, determined by the formula: Cache Line Number = (Main Memory Block Number) modulo (Number of Lines in Cache).

Fully Associative Mapping

A flexible mapping technique where a block of main memory can map to any line of the cache that is freely available at that moment.

K-way Set Associative Mapping

A combination of direct and fully associative mapping where cache lines are grouped into sets, and a main memory block maps to a specific set but any line within it.

Virtual Memory

A concept that provides the illusion of a large main memory equal to the capacity of secondary storage, allowing programs to exceed the size of physical RAM.

Address Space

The set of virtual addresses used by programmers in a virtual memory system.

Memory Space

The set of actual physical locations or physical addresses available in the main memory.

Paging

A management technique where the address space is divided into equal-sized groups called pages, and memory space is divided into blocks or page frames.

I/O Interface

A special hardware component that provides a method for transferring information between internal storage and external I/O devices, resolving differences in signal values and speeds.

Isolated I/O

A configuration where the CPU uses separate address spaces and separate read/write control lines for memory and I/O devices, typically using Instructions like IN and OUT.

Memory Mapped I/O

A configuration where memory and I/O devices share the same address space and use a single set of read/write control lines.

Programmed I/O

A data transfer mode requiring constant monitoring (polling) of the I/O device by the CPU until the device is ready for the transfer.

Interrupt-Initiated I/O

A data transfer mode where the CPU executes other tasks until the interface issues an interrupt request signal once data is available.

Direct Memory Access (DMA)

A technique used to transfer large blocks of data at high speed directly between I/O devices and main memory, temporarily disabling the CPU to bypass it.

DMA Controller (DMAC)

A chip that manages direct memory transfers by borrowing the address, data, and control buses from the CPU.

Traps

Another name for software interrupts that arise from illegal or erroneous use of an instruction or data.

Maskable Interrupt

A hardware interrupt that can be delayed when a higher-priority interrupt has occurred to the processor.

Daisy-Chaining Priority

A serial priority interrupt system where all devices requesting an interrupt are connected in a chain, with the device closest to the processor receiving the highest priority.