Communication for Embedded Systems

Why does longer wire force lower baud rates?

• Wires have capacitance (longer wire = higher capacitance = slower rise time)

• Digital signal = sum of harmonics; band-limited channel cannot transmit high harmonics

• Edges round off, bit boundaries blur - no solution except dropping rate

What are the four wired communication standards compared?

• UART (asynchronous, point-to-point)

• SPI (synchronous, master-slave)

• I²C (synchronous, multi-master)

• CAN (asynchronous differential, automotive)

UART wires and clock

• Two wires (TX, RX)

• No clock (asynchronous)

• Both ends must agree on baud rate in advance (9600, 115200)

UART frame format

• Start bit (0)

• 5-9 data bits

• Optional parity

• 1-2 stop bits

• Standard: 8N1 (8 data, no parity, 1 stop)

UART devices and use cases

• Point-to-point only

• 3.3V and 5V systems need level shifter

• Used for PC debugging, GPS modules, Bluetooth-serial

What happens if UART baud rates disagree?

• Data silently corrupted

• No error detection unless parity enabled

• Both ends must agree in advance

SPI wires

• Four wires: MOSI, MISO, SCLK

• Plus one SS/CS line per slave

• Synchronous (clock provided by master)

SPI characteristics

• Very fast (tens to hundreds of MHz)

• Full-duplex, push-pull drivers

• One master, many slaves (each extra slave needs GPIO pin for SS)

SPI use cases

• SD cards

• Displays

• ADCs

• External flash

I²C wires

• Two wires: SDA (data), SCL (clock)

• Open-drain with external pull-up resistors

• Wired-AND logic

I²C addressing and speed

• 7-bit addresses → up to 128 devices

• Standard 100 kHz, fast 400 kHz, high-speed up to 3.4 MHz

• Multi-master, multi-slave on same wires

I²C pull-up resistor trade-off

• Too high: slow rise times (limits speed)

• Too low: wastes current

• Typical: 4.7 kΩ at 100 kHz, 1-2.2 kΩ at 400 kHz

I²C bus arbitration

• If two masters transmit simultaneously

• One that senses low while trying to drive high loses

• Backs off and retries

I²C use cases

• Sensors (IMUs, temperature)

• EEPROMs

• LCDs

• SMBus = I²C for PC-motherboard management

CAN bus origin and wires

• Designed by Bosch in 1986 for automotive

• Two differential wires (CAN-H, CAN-L)

• 120 Ω termination at each end

CAN bus noise immunity

• Differential signalling makes extremely immune to common-mode noise

• Exactly what you want next to ignition system

• Multi-master and message-based

CAN bus arbitration

• Every node sees every message, filters by ID

• Non-destructive arbitration

• Lower message ID (higher priority) wins; other quietly retries

CAN bus features

• Built-in CRC, ACK bits, error frames

• Up to 1 Mbit/s classical CAN

• CAN FD reaches 5+ Mbit/s

Side-by-side comparison: Wires

• UART: 2 wires

• SPI: 4+ wires

• I²C: 2 wires

• CAN: 2 wires (differential)

Side-by-side comparison: Clock

• UART: Async (baud match)

• SPI: Sync

• I²C: Sync

• CAN: Async (bit stuffing)

Side-by-side comparison: Devices

• UART: Point-to-point

• SPI: 1 master, N slaves

• I²C: 128 addresses

• CAN: Multi-master, many nodes

Side-by-side comparison: Speed

• UART: Low–medium

• SPI: High

• I²C: Low–medium

• CAN: Up to ~1 Mbit/s

Side-by-side comparison: Full duplex

• UART: Yes

• SPI: Yes

• I²C: No

• CAN: No

Side-by-side comparison: Noise immunity

• UART: Low

• SPI: Low

• I²C: Low

• CAN: Very high

Side-by-side comparison: Typical use

• UART: Debug, simple links

• SPI: SD cards, displays

• I²C: Sensors, EEPROMs

• CAN: Automotive, industrial

What happens to square waves over long wires?

• Square waves need many high frequency components (Fourier series)

• Capacitors filter out high frequencies

• "Squareness" lost through capacitors → timing issues

Why were historical parallel ports problematic at high speed?

• One line per bit (many wires, large connectors)

• All signals need to arrive at same time

• Capacitance changes based on wire bends → signals arrive at different times

What is UART?

• Universal Asynchronous Receiver/Transmitter

• Serial communication

• 8 bit data, 1 stop bit, no parity (8N1) typical

SPI master-slave architecture pins

• CS (Chip Select): selects which slave to talk to

• SCLK (Serial Clock): master drives clock

• MOSI (Master Out, Slave In)

• MISO (Master In, Slave Out)

What is I²C?

• Inter-chip communication

• Half-duplex

• Up to 5 Mb/s

Sleep mode: Idle

• CPU stopped

• Most clocks still running

• Wake from any interrupt

Sleep mode: ADC noise reduction

• CPU stopped

• Most clocks still running

• Wake from ADC complete or external interrupt

Sleep mode: Power-save

• CPU stopped

• Async timer only running

• Wake from timer or external interrupt

Sleep mode: Power-down

• CPU stopped

• All clocks stopped

• Wake from external interrupt or watchdog

EEPROM write functions compared

• eeprom_write_byte(): always writes (burns cycle even if unchanged)

• eeprom_update_byte(): reads first, writes only if different (preferred)

• AVR EEPROM rated for ~100,000 write cycles per cell