Fetch Cycle [FDE Cycle, Part 1]

Fetch Stage: BP (1)

PC to MAR: The address of the next instruction is copied from the PC to the Memory Access Register (MAR)

Fetch Stage: BP (2)

MAR TO RAM: The address is sent via the address bus to Memory (RAM)

Fetch Stage: BP (3)

RAM TO MDR: The instruction stored at that address is sent back to the Memory Data Register (MDR) via the Data Bus

Fetch Stage: BP (4)

The instruction is then moved to the Current Instruction Register (CIR) to wait for the Decode stage of the FDE cycle

Fetch Stage: BP (5)

The PC is incremented (PC + 1) so it’s ready for the next cycle