mps pilgan

ARR (Auto-Reload Register)

Sets the period of the timer, defining the PWM signal's period.

PSC (Prescaler Register)

Divides the input clock frequency to achieve the desired timer counting rate.

CCR (Capture/Compare Register)

Defines the value at which the timer will change the output level, setting the PWM duty cycle.

Macros

MODIFY_REG, SET_BIT, CLEAR_BIT - Used to modify specific bits in registers.

Status Register (SR)

Indicates timer events like counter overflow and capture/compare events for interrupt handling.

Duty Cycle

Fraction or percentage of one period in which the PWM signal is active.

Interrupt

Signal to the processor indicating an event needing immediate attention.

Interrupt Handler

Code responding to specific interrupt requests, temporarily pausing the main program.

Interrupt Request (IRQ)

Event triggering an interrupt, leading to ISR execution.

Interrupt Vector Table

Maps each interrupt request to its corresponding ISR for handling.