Second half CMOS Quizzes

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Last updated 8:12 PM on 4/15/26
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32 Terms

1
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T/F: Copper can directly contact silicon without any additional materials in modern processes

False

2
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T/F:Diffusion runners are preferred for long wires because they have low resistance

False

3
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T/F: In modern processes, the aspect ratio (AR = t/w) of wires is typically much less than 1

False

4
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T/F: Using repeaters always reduces both delay and energy consumption

False

5
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Which parameter defines wire pitch?

w + s

6
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Total wire capacitance is composed of:


Top + Bottom + 2×Adjacent capacitance

7
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Which is NOT a common method to reduce crosstalk?


Shield wires

Increase spacing

Decrease spacing

Ensure neighbors switch at different times

Decreasing Spacing

8
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What is the key difference between volatile and non-volatile memory?

Volatile memory loses data without power

9
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Which of the following is volatile memory?

DRAM

ROM
SRAM
SSD

DRAM and SRAM

10
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Which memory type can’t be written to multiple times?

ROM

11
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What does EEPROM use to store data?

Floating-gate transistors

12
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Which of the following about SRAM is correct?

Memory unit layout size is small compared to other memories

There is a precharge before reading process

It needs constant refreshing

Data will be lost after reading operation

All of the above

13
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(T/F) One bit SRAM has 4 transistors

False

14
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(T/F) To read from an SRAM, both bitline and bitline bar need to be precharged before turning on wordline

True

15
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(T/F) During the reading process, one of bitline and bitline bar will stay high and the other will go low

True

16
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(T/F) To write to an SRAM, you only need to write the data in from bitline or bitline bar side

False

17
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(T/F) SRAM is widely used for on-chip memory because it’s fast and also small in area

False

18
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(T/F) SRAM can be scaled down easily into the most advanced technology node because it’s a ratioed circuit

False

19
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To ensure SRAM write operation success

Access transistor needs to be larger than pull up transistor

20
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To ensure read success of SRAM

Pull down transistor needs to be larger than access transistor

21
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(T/F)More SRAM cells connected to bitline and bitline bar means shorter reading time

False

22
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(T/F)For an 8 column, 32 row SRAM array, you need 32 precharge circuits

False

23
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(T/F) SRAM row decoder is necessary, but column decoder/mux is optional depending whether one bit or one row data is accessed during reading process

True

24
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(T/F) It’s always a good practice to keep the write driver transistors as small as possible due to power and area concerns

False

25
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(T/F)Reading sensing amplifier is a differential amplifier and should be enabled and turned on when either read enable or write enable signal is asserted.

False

26
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(T/F)Testing normally costs less compared to chip design and fabrication.

False

27
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(T/F)Most chip failures after fabrication are due to logic bugs rather than electrical failures.

True

28
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(T/F)The stuck-at fault model assumes nodes can be stuck at either logic 0 or logic 1.

True

29
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(T/F)Good observability and controllability increase the number of test vectors required.

False

30
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Which of the following is NOT part of the testing process discussed?

Manufacturing test

Logic verification

Compiler optimization

Silicon debug

Compiler Optimization

31
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What is the main purpose of Shmoo plots?

Diagnose failures by varying voltage and frequency

32
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Which of the following best describes observability?

Ability to measure internal nodes from output pins