COA (comprehensive)

Throughput

A key performance metric defined as Throughput = 1 / max delay, emphasizing efficiency in data processing.

% Increase in Throughput

Computed using the formula (t2 - t1) / t1, where t1 and t2 are throughput values from different phases.

SIMD

• Single Instruction Multiple Data;

• A parallel processing method where multiple processing units execute the same instruction on different data.

Latency Ratio

A metric used to measure the performance of cache memory, reflecting the efficiency of data retrieval.

RAM

Random Access Memory; volatile memory that temporarily stores data and loses all information when powered off.

Cache

A memory buffer that accommodates speed differentials, providing faster access rates for frequently used data.

Associative Memory

Also known as content-addressable memory, allows access based on content rather than memory address.

Memory Hierarchies

Organization of memory types such as registers, cache, primary RAM, and secondary disk memory for data management.

PSW (Program Status Word)

An essential component saved in the stack during an interrupt, representing the state of the executing process.

Types of Interrupts

Classified into software interrupts, initiated by specific instructions, and hardware interrupts, triggered by external events.

Polling Method

An efficient method for managing multiple interrupts, allocating resources based on current task needs.

Bit-time

Time interval between adjacent bits.

FIFO buffer

A structure used to implement an instruction pipeline.

Cache hit ratio

Calculated using (T2 - Tavg + T1) / T2, measuring the performance of the cache system.

Daisy chain mechanism

A method where devices are connected using a single request line prioritized by the interrupting device's priority.

Write-back

Method for updating the main memory as soon as a word is removed from the cache.

Interrupt Vector

The starting address sent by the device in vectored interrupts.

2's complement

A mathematical representation for signed integers in binary form.

Data hazards

Occurrences when an instruction reads a register that a previous instruction overwrites in a future cycle.

Microcomputer

A system that includes at least a microprocessor, program memory, data memory, and I/O.

Flip Flop

A circuit used to store one bit of data.

Auxiliary Memory

Slower access units that trade speed for greater storage capacity and data stability.

Cache block size

The size of the data block stored in cache memory, significant for offset calculations.

Register Memory

Memory with the lowest access time in computer architecture.

TRAP

A non-maskable interrupt requiring immediate attention from the processor.

ORG and END

Not considered machine instructions in programming.

RISC architecture

An architecture where memory access is limited to specific instructions like JMP and MOV.

Microprocessor capacity

The maximum addressing capacity determined by its database and address base size.

Excess 3 code

A type of binary-coded decimal (BCD) that is not a weighted code.

Cache Size

Determined by the number of lines and block size, impacting cache performance.

Priority Encoder

Component that processes the priority of devices based on interrupt registers and mask registers.

N instruction pipelining

Time taken is calculated as k + (n - 1) cycles in a pipelined processor.

Instruction Access Time

T2 = access time without cache, Tavg = access time with cache, T1 = access time of memory.

Speeds and Latency

The performance of cache memory often measured in terms of latency ratio.

Bit Representation

K bit field can specify any one of 2^k registers.

Microcomputer Features

Often includes additional components like timers and analog-to-digital converters.

Memory Buffer

Used in cache to accommodate speed differentials between processor and memory.

Circuit Storage Elements

Flip Flops and registers are key components in data storage.

Addressing Capacity

16 bit database and 32 bit address base yield a maximum of 4G addressing.

Memory Leslie

Used to describe characteristics and design considerations in RISC processors.

Cache Performance Measurement

Frequently assessed through metrics like hit ratio and latency ratio.

Volatile Memory

Type of memory that loses its data when the power is turned off.

Programming Concept

Using ORG and END directives for defining the start and end of a program in assembly language.