COA (comprehensive)
1. Throughput = 1 / max delay
2. % increase in throughput = (t2 - t1) / t1
T2 = max throughput in stage 2
T1 = max throughput in stage 1
3. SIMD-Single Instruction Multiple Data-->includes many processing units under the
supervision of a common control unit
4. Bandwidth=Rate of data lines Number of data Lines; Rate of data lines = 1 / (cycles
time of each cycle)
5. RAM is volatile
6. Flip Flop is the circuit used to store one bit of data
7. Excess 3 code is not a weighted code
8. Cache hit ratio = (T2 - Tavg + T1) / T2; T2 = access time w/o cache, Tavg = access time
with cache, T1 = Access time of memory
9. Wire Through Technique-cache memory
10. PSW is saved in stack when an interrupt occurs
11. Memory unit accessed by content is called associative memory
12. Time interval between adjacent bits is called bit-time
13. An instruction pipeline can implemented by means of FIFO buffer
14. The performance of cache memory is frequently measured in terms of a quantity called
Latency ratio
15. TRAP is a non-maskable interrupt
16. ORG AND END are not machine instructions
17. The maximum addressing capacity of a micro processor which uses 16 bit database &
32 bit address base is 4G
18. a K bit field can specify any one of 2k registers
19. what characteristic of ram memory makes it not suitable for permanent storage?---> it is
volatile
20. Memory access in RISC architecture is limited to instructions--->JMP and MOV
21. Data hazards occur if an instruction reads a Register that a previous instruction
overwrites in a future cycle. We must eliminate data hazards of pipelining that produce
incorrect results.
22. The term microcomputer is used to describe a system that includes a minimum of a
microprocessor, program memory, data memory, and input-output (I/O). Some
microcomputer systems include additional components such as timers, counters,
analog-to-digital converters, and so on.
23. CPU doesn't perform data transfer
24. A stack is a set of memory locations in R/WM reserved for storing information
temporarily during the execution of computer
25. interrupts which are initiated by an instruction are software
26. Register memory has the lowest access time
27. A memory buffer used to accommodate a speed differential is called Cache
28. Auxiliary memory units are among computer peripheral equipment. They trade slower
access rates for greater storage capacity and data stability. Auxiliary memory holds
programs and data for future use,and, because it is nonvolatile (like ROM), it is used to
store inactive programs and to archive data.
29. 2's complement number : 1 --> 0 --> 1 --> 0 --> 1 --> 0 --> 1 --> 0
Booth's encoding : -1 +1 -1 +1 -1 +1 -1 0
Hence the required Booth's encoding of -86 : -1 +1 -1 +1 -1 +1 -1 0
30. In vectored interrupts, how does the device identify itself to the processor?
Explanation: By sending the starting address of the routine ,the device ids ,the routine
required and thereby identifying itself.
31. when dealing with multiple interrupts Polling method is the best
32. The code send by the device in vectored interrupts is 4-8 bits long
33. The starting address send by the device in vectored interrupts is called Interrupt Vector
34. The process indicates to the devices that it is ready to receive interrupts by activating the
interrupt ACK line
35. Vectored interrupts is possible and multiple interrupting devices is not possible for a CPU
having a single interrupt request line and single interrupt grant line.
36. In the Daisy chain mechanism, all the devices are connected using a single request line
and they’re serviced based on the interrupting device’s priority.
37. In a parallel priority system, the priority of the device is obtained by adding the contents
of the interrupt register and the mask register.The added output of the bits of the
interrupt register and the mask register is set as an input of Priority Encoder
38. The range of actual exponent in the IEEE single precision standard for floating point
numbers:-126 to 127
39. The method for updating the main memory as soon as a word is removed from the
Cache is called write-back
40. cache block size is 16 bytes, so block or word offset is 4 bits. i.e log2(cache block
size)=word or block offset=OFFSET
line/index offset=log2(cache size/block size)=SET
TAG bit size= processor address size - (line offset + word offset)
41. bytes occupied by:near=2 far=4 huge=4
42. To perform 'n' 'instructions' in a 'pipelined processor' time taken is k + (n - 1)
cycles,where k is the number of segments.
45. Size of Memory = No of words (Addresses) * No of bits per word
46. Characteristics used in the design of RISC processor:
● Register to Register Arithmetic operations
● Hardwired control unit
Throughput: Throughput is a key performance metric defined as ext{Throughput} = rac{1}{ ext{max delay}} , emphasizing efficiency in data processing and task management.
% Increase in Throughput: The percentage increase in throughput can be computed using the formula rac{(t2 - t1)}{t1} , where and represent throughput values from different phases or configurations, aiding in system optimization assessments.
SIMD: Single Instruction Multiple Data is a parallel processing method where multiple processing units execute the same instruction on different pieces of data, significantly enhancing computational performance in applications such as graphics processing.
Latency Ratio: This metric is crucial in measuring cache memory performance, reflecting the efficiency of data retrieval processes.
Memory and Storage:
RAM: Random Access Memory (RAM) is volatile memory that temporarily stores data and instructions, losing all stored information when powered off. Its speed significantly impacts system performance during data processing tasks.
Cache: A cache serves as a memory buffer that accommodates the speed differentials between the processor and main memory, offering faster data access rates for frequently used information.
Associative Memory: Also known as content-addressable memory, this allows data access based on content rather than memory address, enhancing search efficiency.
Memory Hierarchies: The hierarchy in memory organization includes various types, such as registers, cache, primary (RAM), and secondary (disk) memory, each serving different purposes in data management and access speed.
Interrupts and Processor Behavior:
PSW (Program Status Word): The PSW is an essential component saved in the stack during an interrupt, representing the state of the executing process and facilitating proper handling of subsequent instructions after the interrupt.
Types of Interrupts: Interrupts can be classified into software interrupts, initiated by specific instructions, and hardware interrupts, triggered by external events, each necessitating different handling strategies.
Polling Method: This method is efficient in managing multiple interrupts, ensuring that system resources are allocated based on current task needs.