Structure and Function of the Processor

algorithm

process or set of rules to be followed or calculated to solve problems, especially by a computer

decomposition

breaking down a large problem into smaller, more manageable parts

abstraction

removing unnecessary details from a problem to allow focus on essential components

pseudocode

step-by-step descriptions of an algorithm written in simple english words using a code-like structure

why use pseudocode

• planning before writing actual code

• makes the logic easier to understand

• reduces logical errors before implementation

differences between pseudocode and an algorithm

• algorithms only use simple english-like words → pseudocode uses reserved keywords

• algorithms are a sequence of steps → pseudocode is just fake code, using code-like structure

• algorithms have strict syntax rules → pseudocode has certain rules, but less

• algorithms can be difficult to understand and interpret → pseudocode is easy to understand and interpret

characteristics of a good algorithm

(CITEE)

• clear and precisely stated steps

• allows invalid inputs (without crashing)

• terminates at some point, when needed

• efficient, and in as few steps as possible

• easy to maintain and understandable by others (for modification)

sorting algorithms (3 types)

• merge: splitting and rejoining in order

• insertion: having two lists: unordered and ordered list

• bubble: comparing adjacent values and swapping if needed

searching algorithms (2 types)

linear: comparing each value, one by one

binary: compares middle value, then uses > or < to half the number of values, repeat→ MUST BE IN ASCENDING/ALPHABETICAL ORDER FIRST

CPU

process data and instructions by constantly repeating the FDE cycle

CU

coordinates the activity of all other components and the flow of data and instructions

ALU

performs all arithmetic, logic and shift operations in the cpu

register, and all 5 dedicated registers

super-fast memory that temporarily store data

PC

CIR

MAR

MDR

ACC

PC (register)

stores the memory address of the next instruction to be fetched from RAM

MAR

stores the memory address to be fetched from RAM, may be instruction or data

CIR

holds current instruction, splitting it into opcode and operand

MDR

holds the data instruction that was fetched from main memory into the cpu

ACC

stores data currently being processed and the result of calculations or logical operations

CPU buses

a series of connectors between internal components

→ typically consist of 8,16,32,64

3 types of buses

• control bus

• data bus

• address bus

5 different types of bus signals

• memory read

• memory write

• bus request

• bus grant

• clock

computer

electronic device that takes input, processes data and delivers output

(FDE CYCLE) fetch stage

• PC is checked

• address stored in the PC is copied to the MAR

• address is sent along address bus to main memory → waits to receive signal from control bus

• CU sends a specific signal (e.g. read, plus, etc) along the control bus to main memory

• data is then sent along the data bus to MDR

• data in MDR copied into CIR

• PC incremented by 1

→ fetch stage complete

operode and operand

operode: what to do

operand: what to do it to

(FDE CYCLE) decode stage

• the instruction is decoded (which could be to load, plus, etc) and is to be stored into the acculumator

(FDE CYLE) execute stage

• carries out the decoded instruction

may involve:

→ ALU for calculations or logical

→ data movement

→ branching / jumps