EE 301 Homework 3: Sequential Circuit Timing and Pipeline Analysis

Vocabulary and timing equations covering digital pipeline analysis, setup and hold constraints, clock skew, and minimum clock period derivations.

Setup Time ($t_{\text{setup}}$)

The minimum time before the clock edge that the data input must remain stable, given as $25\,\text{ps}$.

Hold Time ($t_{\text{hold}}$)

The minimum time after the clock edge that the data input must remain stable, given as $25\,\text{ps}$.

Clock-to-Q Delay ($t_{\text{clk-q}}$ / $t_{\text{cq}}$)

The time required for the flip-flop output $Q$ to reflect the input data after the arrival of a clock edge, specified as $10\,\text{ps}$.

Clock Skew ($t_{\text{skew}}$)

The variation in clock arrival times between different flip-flops in a synchronous system, given as $4\,\text{ps}$ in Question 2.

Setup Time Inequality

The timing constraint $t_{\text{cq}} + (t_{\text{comb}})_{\max} \le T_{\text{clock}} + t_{\text{skew}} - t_{\text{setup}}$, rearranged to find minimum period as $T_{\text{clock}} \ge t_{\text{cq}} + t_{\text{comb},\max} + t_{\text{setup}} - t_{\text{skew}}$.

Minimum Clock Period ($T_{\min}$ for Question 2)

The minimum allowable period of $341\,\text{ps}$, dictated by the critical path through flip-flop 1 and $CL_1$ ($T \ge 10 + 310 + 25 - 4 = 341\,\text{ps}$).

Buffer Insertion for Hold Violations

The process of fixing hold time violations by inserting delay buffers with $t_{\text{pd}} = t_{\text{cd}} = 2\,\text{ps}$ along the data path.

Path 2 Period Requirement (Question 2)

The timing limit through combinational block $CL_2$, evaluated as $T \ge 10 + 260 + 25 - 4 = 291\,\text{ps}$.

Path 3 Period Requirement (Question 2)

The timing limit through flip-flop 5 and combinational block $CL_3$, evaluated as $T \ge 10 + 100 + 25 - 4 = 131\,\text{ps}$.

Combinational Propagation Delay ($t_{p,\max}$)

The maximum delay through a combinational logic block, representing the worst-case path between sequential elements.

Combinational Contamination Delay ($t_{p,\min}$)

The minimum delay through a combinational logic block, representing the fastest possible path used to evaluate hold time constraints.