05: Instruction Set Principles & Machine Models

Hardware software contract

the ISA is the _ _ _

IC, CPI

ISA fixes the iron-law inputs

Machine Model

five design axes today (1)

Operands

five design axes today (2)

Addressing

five design axes today (3)

Encoding

five design axes today (4)

Byte Order

five design axes today (5)

Stack

operands implicit on top of stack (PUSH/POP/ADD)

Accumulator

one implicit register one explicit memory operand

Register memory

ALU ops may name a memory operand directly (CISC)

Load store

ALU touches registers only; memory via LOAD/STORE (RISC)

Complex Instruction Set Computer

meaning of CISC

Reduced Instruction Set Computer

meaning of RISC

Code Size

stack or accumulator win one _ _

Memory

but every operand round-trips through _

Simple, Uniform, Pipelines Cleanly

load-store uses more instructions, yet each is _ _ and _ _

Registers are fast

why load-store won? (1)

Memory is bottleneck

why load-store won? (2)

Read Write Register

ALU ops _ _ _ only, why load-store won? (3)

At Most One Memory

_ _ _ _ access per instruction, why load-store won? (4)

Hot Values, Memory Traffic

a large register file keeps _ _ on-chip, cutting _ _ , why load-store won? (5)

Simple Decode, Short Cycle, Easy Pipelining

uniform instructions -> _ _ | _ _ | _ _

Fetch, Decode, Pipeline

fixed length, trivial to _ _ and _

Variable length

denser code, but decode is a serial puzzle

registers and immediate range

encoding sets a hard limit: field widths cap _ _ _ _

Regularity, Same place

_ is a feature – put operand fields in the _ _ every time

Decoder

reads registers before it finishes identifying the instruction

Scrambled, Stay Put

immediates are _ across bits purposely so the register fields _ _

Big endian

MSB at the lowest address (network order)

Most Significant Bit

meaning of MSB

Little endian

LSB fist (x86, ARM, RISC-V)

Least Significant Bit

meaning of LSB

Byte Order

need to check interoperability