cse 341 torture

first cycle

instruction fetch and increment pc

second cycle

instruction decode and register fetch

third cycle

execution, memory addr computation, or branch completion

fourth cycle

memory access or r type instruction completion step

fifth cycle

memory read completion step

[second cycle] ALUOut =

PC + (sign extend IR « 2)

Each cycles is one of:

alu operation, register file access, memory access

for multicycle, data needed in a later clock cycle must be

stored in a register

cycles needed per instruction:

1. load

2. store

3. alu

4. branch

5. jump

5 4 4 3 3

Write Control

pc memory registers ir

read control

memory

alu control

refer to single cycle datapath designm

multiplexors

two 2 input mux, one 4 input mux

[jump and branch]

PC Source:

ALU Output =

PC + 4

[jump and branch]

PC Source:

ALUOut register =

branch register

[jump and branch]

PC Source:

IR0…26 concatenated w/ upper 4 bits of pc =

jump target

[jump and branch]

Ctrl signals:

PCWrite =

PCWriteCond =

unconditional conditional

PCWriteCond is combined with ____ to control…

zero pcwrite

regdst

0 =

1 =

rt selects write reg num, rd selects write reg num

regwrite

0 =

1 =

none, gpr data written

ALUSrcA

0 =

1 =

pc selected as first operand, a reg selected as first operand

MemWrite

0 =

1 =

nothing, data read from memory

MemtoReg

0 =

1 =

write data input supplied by ALUOut reg, rite data input supplied by MDR

IorD

0 =

1 =

pc supplied addr to mem unit, aluout register supplies addr to mem unit

IRWrite

0 =

1 =

none, output of mem written to ir

PCWrite

0 =

1 =

none, pc written

PCWriteCond

0 =

1 =

none, pc written if zero output from alu is active

ALUOp

00 =

01 =

10 =

add, sub, funct field deteremines operation

ALUSrcB (selects 2nd input to ALU)

00 =

01 =

10 =

11 =

b reg, 4, sign ext lower 16 bits of ir, sign ext lower bits of ir * 4

PCsource (selects source of pc data)

00 =

01 =

10 =

alu output (PC + 4), aluout contents (branch target), ir[25…0] * 4 concat w pc[31..28] (jump target)

lw and sw have an ____

offset

loads: base reg must be read from…

register file

stores: base reg & val to be stored must be…

read from reg file

16 bit offset is stored in… [for load store]

instruction

branch offset needs to be…

left shifted