Digital Circuits Exam II

easy stuff but way too much material to cram any other way.

[U4] What does a full adder do?

Adds three input bits (X, Y, and carry-in) and produces a sum bit and a carry-out bit.

[U4] How is an n-bit parallel adder built?

From n full adders, with each stage's carry-out connected to the next stage's carry-in (ripple carry). All bits of A and B are applied at the same time.

[U5] How do you get the minimum sum-of-products from a map?

Group the 1s (X's may be used as 1s) into the largest possible groups, include all essential prime implicants, then add the fewest other prime implicants needed to cover all remaining 1s.

[U5] How do you get the minimum product-of-sums from a map?

Group the 0s (X's may be used as 0s) into the largest possible groups, read each group as a sum term, and AND the sum terms together.

[U6] What is the Quine-McCluskey method used for, and why?

A tabular method for finding all prime implicants and a minimum SOP. It is used because it is systematic and can be programmed, and it works for functions with many variables where Karnaugh maps are impractical.

[U7] What is an AND-OR circuit?

A two-level circuit where the first level is AND gates and the second level is a single OR gate, implementing a sum-of-products.

[U7] Why do designers use NAND-NAND or NOR-NOR circuits?

NAND and NOR gates are universal and are simpler, faster, and cheaper to build in hardware than AND and OR gates. A NAND-NAND circuit is equivalent to AND-OR, and NOR-NOR to OR-AND, so only one gate type is needed.

[U8] What is fan-in?

The number of inputs to a gate.

[U8] What is a static 1-hazard?

When an input changes, the output should stay at 1 but momentarily goes to 0 (a glitch) because of unequal gate delays.

[U8] What is a static 0-hazard?

When an input changes, the output should stay at 0 but momentarily goes to 1 because of unequal gate delays.

[U8] What is a dynamic hazard?

When the output should change once (0 to 1 or 1 to 0) but changes three or more times (e.g. 0-1-0-1) because of unequal gate delays.

[U8] How do you build a two-level SOP circuit free of static and dynamic hazards (single input changes)?

Include every prime implicant (add the consensus terms that cover adjacent groups). A two-level SOP with all prime implicants has no static 1-hazards and no dynamic hazards, and a two-level circuit never has static 0-hazards.

[U8] What does a four-valued logic simulator use for its values?

0, 1, X (unknown or uninitialized), and Z (high impedance or not driven). It shows what a gate output will be when its inputs are unknown or undriven.

[U8] What does X mean in a four-valued simulator?

An unknown value, such as an uninitialized signal or a conflict between drivers. A gate output is X when its inputs do not determine the output.

[U8] What does Z mean in a four-valued simulator?

High impedance, meaning the signal is not being driven (disconnected).

[U10] In VHDL, what is an entity?

The interface description of a module (its name and ports), similar to an opaque box.

[U10] In VHDL, what is an architecture?

It defines a way to implement (describe the inside of) an entity.

[U10] What is a VHDL dataflow description?

A description using concurrent signal assignment statements (e.g. D <= A AND (NOT B);) to represent logic equations. The order of the statements doesn't matter.

[U10] How do you build a VHDL module by interconnecting components?

Declare each component, declare internal signals, and instantiate each with a port map that connects its ports to signals and ports.

[U10] What does "open" mean in a VHDL port map?

The output port is left unconnected.

[U10] What operator is used for concatenation in VHDL?

& (ampersand)

[U10] Which VHDL data type is only FALSE or TRUE?

boolean

[U10] What are the main VHDL types to recognize?

bit, bit_vector, boolean, integer, and time.

[U10] Which VHDL type holds values like 20 ns?

time

[U10] How do you define an array type in VHDL?

type myArrayType is array (0 to 1) of bit_vector(0 to 3);

[U10] How do you declare and initialize a signal of an array type?

signal myArray: myArrayType := ("0000", "0001");

[U10] What is IEEE Standard Logic (std_logic)?

A multi-valued logic type (IEEE 1164) with values such as 0, 1, X, Z, and U. std_logic_vector is its array form, and with overloaded operators it can be used to do arithmetic.

[U20] What is a test bench?

VHDL code that is written to test another VHDL module

[U20] What data type is the index variable in a VHDL for loop?

integer

[U20] Can a VHDL for loop index be explicitly declared?

No. It is declared implicitly by the loop and exists only inside the loop.

[U11] What is a sequential switching circuit?

A circuit whose outputs depend on the present inputs and on past inputs (its state). It has memory.

[U11] What are latches and flip-flops?

The basic memory elements (one-bit storage devices) of sequential circuits.

[U11] What is a common way to synchronize all flip-flops in a synchronous digital system?

A clock signal.

[U11] What is a memory element with no clock input often called?

A latch

[U11] What is feedback in a sequential circuit?

A circuit output connected back to an earlier input, which makes memory possible.

[U11] How do you build a set-reset latch from NOR gates?

Two cross-coupled NOR gates, with each gate's output fed to an input of the other.

[U11] How does S affect Q in the NOR set-reset latch?

S = 1 (with R = 0) sets Q to 1. Q stays 1 after S returns to 0.

[U11] How does R affect Q in the NOR set-reset latch?

R = 1 (with S = 0) resets Q to 0. Q stays 0 after R returns to 0.

[U11] What happens when S = R = 0 in an SR latch?

The latch holds its previous value.

[U11] What does present state and next state mean?

Present state is the current value of the memory element (Q). Next state is the value it will have after the inputs/clock take effect (Q+).

[U11] Why is a gated D latch called a transparent latch?

While the gate (enable) is 1, Q follows D, so the input passes straight through to the output.

[U11] Gated D latch: what is Q+ when G = 0? When G = 1?

G = 0: Q+ = Q (holds). G = 1: Q+ = D.

[U11] What is the rising (positive) edge of a clock?

The transition from 0 to 1.

[U11] What is the falling (negative) edge of a clock?

The transition from 1 to 0.

[U11] What does it mean for a D flip-flop to be rising-edge triggered?

It copies D to Q only at the 0-to-1 clock transition (Q+ = D) and holds its value at all other times.

[U11] How do you draw the clock input for a rising-edge versus a falling-edge D flip-flop?

Rising-edge: a small triangle at the clock input. Falling-edge: a triangle with a bubble (inversion circle) at the clock input.

[U11] How do you build a rising-edge D flip-flop from two gated D latches?

A master-slave arrangement: the first latch (master) gets the inverted clock and the second (slave) gets the clock. The master's output feeds the slave's D input.

[U11] T flip-flop truth table?

T = 0: Q+ = Q (hold). T = 1: Q+ = Q' (toggle).

[U11] In an asynchronous sequential circuit, when can the state change?

Any time an input changes, with no clock.

[U11] What is a state machine?

A model of a sequential circuit with a finite number of states, where the inputs and present state determine the next state and the outputs.

[U11] Asynchronous versus synchronous state machine?

Synchronous: state changes only at clock edges. Asynchronous: state changes immediately in response to input changes, with no clock.

[U11] Why study asynchronous state machines?

They show how latches and flip-flops actually work, and are used where there is no clock (e.g. interfacing between clock domains, speed, low power).

[U11] What serves as the memory in an asynchronous finite state machine?

The feedback loops with their propagation delays.

[U11] What is an essential hazard?

An error caused by a single input change being seen by different parts of the circuit at different times (a race between the input change and the state-variable feedback), so the circuit goes to the wrong state.

[U11] What are essential hazards a property of?

The sequential function (the flow table/state machine), not the particular gate-level implementation. They are fixed by adding delay, not by changing the logic.

[U10] VHDL type bit: what values does it hold? Example?

A single binary value, '0' or '1' (single quotes). Example: signal A : bit := '1';

[U10] VHDL type bit_vector: what is it? Example?

An array of bits (double quotes for the value). Example: signal B : bit_vector(3 downto 0) := "1010"; The bit B(3) is '1' and B(0) is '0'.

[U10] VHDL type boolean: what values does it hold? Example?

Only FALSE or TRUE (no quotes). Example: signal Ready : boolean := TRUE;

[U10] VHDL type integer: what values does it hold? Example?

Whole numbers (positive or negative). Example: signal Count : integer := 5;

[U10] VHDL type time: what values does it hold? Example?

A time value with a unit such as ns, ps, or us. Example: G1 <= A AND B after 20 ns;

[U10] Which VHDL types use single quotes and which use double quotes for values?

Single quotes for a single bit, e.g. '1'. Double quotes for a bit_vector, e.g. "1010". boolean and integer values use no quotes (TRUE, 5).

[U10] Which VHDL type fits each value: '1', "0110", TRUE, 42, 20 ns?

'1' is bit, "0110" is bit_vector, TRUE is boolean, 42 is integer, and 20 ns is time.