Introduction to Solid-State Electronics and Semiconductor Processing

Vocabulary practice flashcards covering the history of semiconductor electronics, transistor architectures, physical principles, fabrication processes, Moore's Law, and micro-electro-mechanical systems (MEMS).

First Solid-State Transistor

A point-contact device invented in 1947 at AT&T Bell Lab by William Shockley, John Bardeen, and Walter Brattain, constructed from a slab of germanium with two gold point contacts fractions of a millimeter apart.

Raytheon CK722

The first commercially successful transistor, introduced in 1953 as a germanium-based PNP low-power transistor.

First Silicon Transistor

The first transistor made from silicon rather than germanium, fabricated in 1954 by Gordon Teal at Texas Instruments (TI).

Integrated Circuit (IC)

A miniaturized electronic system comprised of multiple transistors and interconnects fabricated simultaneously on a common semiconductor substrate, invented in 1958–1959 by Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Semiconductor.

MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor)

A family of field-effect transistors invented in 1962 by Steven Hofstein and Fredric Heiman at the RCA research laboratory that became the foundational device for modern digital integrated circuits due to lower power consumption, small size, and low production cost.

The Traitorous Eight

A group of eight scientists and engineers who left Shockley Labs in 1957 due to William Shockley's management style to found Fairchild Semiconductor, the first company to work exclusively in silicon and the catalyst for Silicon Valley.

Moore's Law

An empirical observation formulated in 1965 by Gordon Moore stating that the number of transistors on integrated circuits doubles approximately every 18 to 24 months (two years).

Moore's Second Law

The observation that the capital cost of building a semiconductor chip fabrication plant (fab) doubles approximately every four years.

Semiconductor Bandgap ($E_g$)

The energy separation between the valence band and the conduction band; small enough in semiconductors that thermal energy at room temperature allows some electrons to jump to the conduction band.

Intrinsic Silicon

Pure crystalline silicon containing approximately $5 \times 10^{22}\,\text{atoms/cm}^3$, yielding an intrinsic carrier concentration of $1.5 \times 10^{10}\,\text{electrons/cm}^3$ in the conduction band at room temperature ($\sim 300\,\text{K}$).

N-Type Doping

The process of intentionally adding Group V impurity atoms (such as Phosphorus, Arsenic, or Antimony) into the silicon crystal lattice to supply excess mobile conduction electrons.

P-Type Doping

The process of intentionally adding Group III impurity atoms (such as Boron) into the silicon lattice to create mobile empty electron states called holes.

Diode

A two-terminal semiconductor P-N junction device that allows electric current to flow primarily in one direction (from P to N), exhibiting a forward turn-on voltage ($V^{\text{on}}$) of approximately $0.6\text{--}0.7\,\text{V}$.

Bipolar Junction Transistor (BJT)

A three-terminal semiconductor device formed by configuring PNP or NPN junctions with controlled dimensions and doping concentrations, used as an amplifier, switch, or digital logic gate.

Microfabrication Central Loop

The recurring sequence of deposition, lithography, and etching performed repeatedly on a silicon substrate to build up layers of an integrated circuit.

Strained Silicon

A technique where silicon lattice spacing is altered—such as by introducing silicon-germanium (SiGe)—to increase carrier mobility and achieve faster electron flow across the transistor channel.

FinFET

A non-planar 3D transistor design featuring a thin vertical semiconductor fin surrounded on multiple sides by the gate, significantly reducing drain-source leakage current and short-channel effects compared to planar FETs.

Gate-All-Around (GAA) FET

An advanced device structure in which the gate electrode completely surrounds the channel (using nanowires or nanosheets) on all four sides to enable scaling down to the $2\,\text{nm}$ technology node and below.

More Moore

The roadmap strategy focused on continued geometrical miniaturization and digital density scaling of baseline CMOS technologies (such as CPU, memory, logic, and System-on-Chip).

More than Moore

The technological diversification trend incorporating non-digital functions—such as analog/RF, high-voltage power, passive components, sensors, actuators, and biochips—into high-value systems through System-in-Package (SiP) solutions.

MEMS (Micro-Electro-Mechanical Systems)

Miniaturized mechanical components, sensors, and actuators fabricated on semiconductor substrates using adapted microelectronics batch-processing techniques.

Digital Micro-Mirror Device (DMD)

An optical MEMS component developed by Texas Instruments containing a two-dimensional array of tiltable aluminum micromirrors positioned over CMOS SRAM cells to modulate light in projection systems.

ADXL202

A dual-axis CMOS integrated micro-accelerometer produced by Analog Devices that uses a capacitive dangling silicon mass to sense acceleration for applications like vehicle stability and seatbelts.

First Solid-State Point-Contact Transistor (1947)

A laboratory device invented at AT&T Bell Laboratories by William Shockley, John Bardeen, and Walter Brattain consisting of a slab of germanium with two gold foil point contacts spaced fractions of a millimeter apart, which earned them the 1956 Nobel Prize in Physics.

Raytheon CK722

The first commercially successful transistor, released in 1953 as a packaged germanium-based $p\text{-}n\text{-}p$ low-power alloy junction device available to electronics hobbyists and engineers.

First Commercial Silicon Transistor (1954)

A device developed by Gordon Teal at Texas Instruments (TI) that replaced germanium with silicon, providing operational stability at significantly higher temperatures.

Invention of the Planar Integrated Circuit (1958–1959)

The miniaturization breakthrough co-invented by Jack Kilby at Texas Instruments (who used germanium with external wire interconnects) and Robert Noyce at Fairchild Semiconductor (who patented silicon planar processing with printed thin-film metallization).

MOSFET Device Origin (1962)

A field-effect device invented by Steven Hofstein and Fredric Heiman at RCA research laboratories whose compact planar footprint, low power consumption, and low manufacturing cost established it as the primary building block for modern digital integrated circuits.

The Traitorous Eight

The group of scientists and engineers (including Robert Noyce and Gordon Moore) who left Shockley Semiconductor Laboratory in 1957 due to William Shockley's erratic management to found Fairchild Semiconductor, pioneering silicon processing and initiating Silicon Valley.

Moore's Law

An empirical trend observed in 1965 by Gordon Moore predicting that the number of transistors packed onto a dense integrated circuit doubles approximately every 18 to 24 months.

Moore's Second Law (Rock's Law)

The economic observation stating that the capital cost of constructing and outfitting a leading-edge semiconductor fabrication facility (fab) doubles approximately every four years.

Microfabrication Central Loop

The fundamental, repeating process sequence composed of thin-film deposition, photolithographic patterning, and material etching repeated across $40\text{--}80$ mask steps to build up multi-layered semiconductor devices.

Intrinsic Silicon Properties at Room Temperature

Pure crystalline silicon with a density of $\rho = 2.33\text{ g/cm}^3$ ($\text{atomic density} \thicksim 5 \times 10^{22}\text{ atoms/cm}^3$), which yields a low intrinsic carrier concentration of $n_i \thicksim 1.5 \times 10^{10}\text{ electrons/cm}^3$ at $T \thicksim 300\text{ K}$.

Material Advantages of Silicon Over Germanium in Integrated Circuits

Silicon features a wider bandgap ($E_g = 1.12\text{ eV}$ vs. $0.67\text{ eV}$), enabling ICs to operate up to $150^\text{ }\text{C}$ (compared to $100^\text{ }\text{C}$ for Ge), naturally grows a water-insoluble and thermally stable passivation oxide ($\text{SiO}_2$ vs. soluble $\text{GeO}_2$), and is the second most abundant crust element ($25.7\text{\%}$ by weight).

Direct vs. Indirect Bandgap Recombination

Direct bandgap materials (e.g., $\text{GaAs}$, $E_g = 1.43\text{ eV}$) recombine electrons and holes without a crystal momentum shift, releasing energy as photons (light); indirect bandgap materials (e.g., $\text{Si}$, $\text{Ge}$) require momentum exchange with the lattice, dissipating energy as phonons (heat) through recombination-generation centers.

Bandgap Engineering in Compound Semiconductors

The technique of tailoring electronic and optical properties by modulating the atomic fractions of compound alloys (such as varying $x$ in $\text{Al}_x\text{Ga}_{1-x}\text{As}$ between $1.43\text{ eV}$ and $2.16\text{ eV}$, or in $\text{Hg}_{1-x}\text{Cd}_x\text{Te}$ between $-0.25\text{ eV}$ and $1.6\text{ eV}$) to construct optoelectronic and heterostructure devices.

Carrier Mobility Disparity Between Silicon and Compound Semiconductors

Compound semiconductors offer substantially higher electron mobility (e.g., $\text{GaAs}$ with \thicksim 8500\text{ cm}^2/\text{V}\boldsymbol{\bar}\text{s} and $\text{InSb}$ with \thicksim 10^5\text{ cm}^2/\text{V}\boldsymbol{\bar}\text{s} compared to silicon's 1350\text{ cm}^2/\text{V}\boldsymbol{\bar}\text{s}), providing faster carrier transit times in high-frequency and microwave devices.

Amphoteric Dopants in Compound Semiconductors

Impurity atoms that act as donors or acceptors depending on the host lattice site they substitute into (for example, silicon in $\text{GaAs}$ serves as a donor on gallium sites, but acts as an acceptor on arsenic sites).

Strained Silicon Channel Engineering

A technique in which silicon is grown epitaxially over a crystal with a larger lattice parameter (such as silicon-germanium, $\text{SiGe}$), applying mechanical stress to the crystal lattice to reduce carrier effective mass and increase carrier mobility.

FinFET (Fin Field-Effect Transistor) Architecture

A non-planar 3D transistor structure featuring a narrow vertical silicon fin embraced on three sides by a gate electrode, mitigating short-channel effects and drain-source leakage currents.

Gate-All-Around (GAA) FET Architecture

An advanced transistor topology featuring stacked horizontal nanosheets or nanowires completely encircled on all four perimeter surfaces by the gate dielectric and gate metal, enabling physical gate length scaling to $2\text{ nm}$ and below.

More Moore vs. More than Moore Scaling

"More Moore" pursues dimensional scaling and density increases of pure digital CMOS logic and memory; "More than Moore" focuses on functional diversification by co-integrating non-digital elements (such as analog, RF, power electronics, sensors, and micro-actuators) inside System-in-Package (SiP) architectures.

MEMS (Micro-Electro-Mechanical Systems)

Miniaturized devices that integrate microscopic mechanical components, moving membranes, and micro-sensors alongside electrical microelectronics on semiconductor wafers using microfabrication batch techniques.

Digital Micro-Mirror Device (DMD)

An optical MEMS component developed by Texas Instruments containing a 2D matrix of tiltable microscopic aluminum mirrors positioned over static CMOS SRAM address cells to redirect light for video projectors and optical displays.

Capacitive Micro-Accelerometer (e.g., ADXL202)

A surface-micromachined dual-axis MEMS inertial sensor featuring a suspended polysilicon proof mass between stationary capacitive plates; acceleration displaces the mass, producing an electrical capacitance shift used in automobile stability and restraint systems.

CMOS Inverter Complementary Architecture

A logic circuit pairing an nMOS pull-down transistor in a p-type substrate with a pMOS pull-up transistor in an n-well, connecting their gates to a common input and their drains to a shared output to prevent static short-circuit DC current draw.

CMOS Substrate and Well Taps

Heavily doped ohmic diffusion regions ($p^+$ in the p-substrate wired to $\text{GND}$, and $n^+$ in the n-well wired to $V_{DD}$) that bias the bulk silicon, eliminate rectifying metal-semiconductor Schottky barriers, and suppress CMOS latch-up.

Six Basic Photolithography Masks of Conventional CMOS

The standard minimal mask set required to construct a basic CMOS inverter: (1) n-well definition, (2) polysilicon gate routing, (3) $n^+$ diffusion, (4) $p^+$ diffusion, (5) dielectric contact vias, and (6) metallization.

Thermal Oxidation of Silicon

A high-temperature furnace process ($900\text{--}1200^\text{ }\text{C}$) utilizing dry oxygen gas ($\text{O}_2$) or wet steam ($\text{H}_2\text{O}$) to oxidize the wafer surface and grow high-purity, insulating silicon dioxide ($\text{SiO}_2$) layers.

Positive Photoresist (PR) Mechanism

A light-sensitive organic polymer spun onto a wafer that undergoes photo-chemical degradation when exposed to ultraviolet radiation, making the exposed areas soluble in a chemical developer solution.

Hydrofluoric Acid (HF) Etch Step

A wet chemical etching procedure with high chemical selectivity that dissolves silicon dioxide ($\text{SiO}_2$) through mask openings while leaving the underlying crystalline silicon substrate unharmed.

Polysilicon Gate Chemical Vapor Deposition (CVD)

The thermal decomposition of silane gas ($\text{SiH}_4$) inside a reactor to deposit a polycrystalline silicon layer over the thin gate oxide, which is subsequently heavily doped to serve as a conductive gate electrode.

Self-Aligned Gate Process

A CMOS processing method where the patterned refractory polysilicon gate serves as an implant barrier mask during source and drain ion implantation, aligning junction edges to channel boundaries without parasitic overlap capacitance.

CMOS Contact and Metallization Processing

The back-end-of-line procedure wherein a thick protective interlayer oxide is deposited, contact cuts are etched down to active gates and diffusions, and aluminum or copper is sputtered and etched to form electrical wires.