CS 250 - EXAM 2 STUDY GUIDE FINAL

Duplexity governs whether the signals being transmitted are distinguishable. T/F

False

Modulation governs whether the transmission are unidirectional or bidirectional T/F

False

The 4B/5B encoding scheme ensure that the translated codes (4-bit to 5-bit encodings) do not result in more han 1 leading 0 and no more than 2 trailings 0's

The 5-bit codes are transmitted using NRZI that performs transitions for 1s

What is the efficiency of the 4B/5B encoding scheme?

80%

What is the efficiency of the Manchester encoding scheme?

50%

Circuit switched networks require circuits and their accompany state to be established BEFORE data can be transferred T/F

True

All communications in networked systems are based on sending and recieving messages i.e. there is no shared memory T/F

True

One advantage of layered systems is that each layer can be chnaged independently of each other T/F

True

Networking stacks are a hardware implementation. i.e. the entire functionality is implemented on chips using NAND gates T/F

False

it is routtine for CPUs to have hundreds of general purpose registers T/F

False

As a side effect of the instruction execution, the CPU also figures out which instruction to fetch and execute next T/F

True

Although it works well for several classes of problems, dividing up a single program so that it can be parallelized ot make use of multiple CPUs is an unsolved problem in the general case T/F

True

For each I/O device, memory-mapped I/O allocates a designated area in the computers memory that acts as its memory map. These one-time configurations are carried out by installer programs. T/F

True

The device driver program bridges the gap between the I/O devices memory map data and the way this data is a ctually rendered on, or generated by, the physcial I/O device. T/F

True

An implementation describes what the module does, while the abstraction describes how it does it. T/F

False

An m-bit CPU means that the computer architecture has m-bit registers, a m-bit address bus, or a m-bit data bus or perhaps ALL three are m-bit. T/F

True

reduced energy requirements translate into power consumption and lower heat generation. T/F

True

the key takeaway in dennary scaling is that the power consumption stays the same with twice the number of transistors with every technology generation (at least up until we started to have increased static power losses.) T/F

True

The Harvard architecture needs two separate memory buses: one for instruction and one for data. T/F

True

Languages such as Java and C# employ a single stage compilation model where the source code is compiled directly into machine language. T/F

False

Code generated by compilers for the C programming language are intermediate bytecodes that is subsequently translated into very efficient machine code well suited for high performance computing and embedded devices. T/F

False

Reading a value form the stack using pop is a lossy operation. T/F

True

Writing an itme into a regular memory location is not a lossy operation. T/F

False

A stack is only accessible from the top. T/F

True

Consider the Stack Machine: From the stacks perspsective, each arithmetic or logical operation has the net impact of replacing the operations operands with the operations result. T/F

True

The stack data structute is based on the First-in-First-out principle. T/F

False. LIFO

There is no such thing as a standalone execution of a statement; statements within a program always execute within the confines of a thread. T/F

True

For any arbitrary calling chain, the only function truly active in the calling chain is the last one. T/F

True

Primitive local variables in a function/method are allocated on the stack. T/F

True

What is the Von Neumann architecture?

A computing system structure that includes a CPU, memory, and I/O devices, where both data and program instructions are stored in the same memory.

Define the Stored Program Concept.

The idea that computer instructions are stored in memory alongside data, allowing the computer to execute a variety of programs on the same hardware.

Explain Direct Mapped Cache.

A caching method where each block of main memory maps to exactly one cache line based on address bits.

What is a Cache Line?

A block of memory brought into the cache, where its size is typically 16 to 64 bytes.

Define N-Way Set Associativity in caches.

A cache organization that allows each block of main memory to map to any of 'N' cache lines in a set, balancing between direct mapped and fully associative caches for efficiency. Better than direct mapped.

Converting Bits to Bytes

Formula: 1 Byte = 8 Bits

Converting Bytes to Kilobytes (KB)

Formula: 1 KB = 1024 Bytes

How do cache hit rates affect performance?

High cache hit rates reduce the need to access slower main memory, thereby increasing overall system performance.

What functions does an ALU (Arithmetic Logic Unit) perform?

The ALU performs basic arithmetic (addition, subtraction) and logical (AND, OR, NOT) operations.

What is the Socket Abstraction?

A programming interface (API) for exchanging data between computers over a network.

Explain the concept of Internet Architecture.

The design principles and standards that underlie the Internet, including protocols for routing and addressing data packets to enable global communication.

What does "Moore's Law" observe?

Every two years, the number of transistors in a dense integrated circuit doubles, historically leading to computers doubling in speed.

What is "Dennard Scaling"?

As transistors get smaller, their power density stays constant, leading to less power use as size decreases.

How do computers handle binary data encoding through signals?

By varying signal frequency, amplitude, or phase to transmit 0s and 1s.

What is "Duplexity" in networking?

It's about how many bit streams can be sent over a link simultaneously and whether data can flow in both directions at once.

What does a "ServerSocket" do in Java networking?

It listens for incoming network connections on a specified port and sets up connections between client and server.

Why is "Memory Mapped I/O" important?

It abstracts the complexity of I/O devices by making them appear as regular memory segments to the CPU.

What are the three common bus types in computer architecture?

Address bus, Data bus, and Control bus.

What does "Manchester Encoding" solve in signal transmission?

It addresses issues like baseline wander and clock recovery by encoding 0s and 1s as signal transitions.

How do "Switched Networks" enable connectivity?

By using intermediary nodes that forward data, allowing for scalable and efficient networking.

Fully Associative Cache:

Any block of memory can be placed in any cache line; highly flexible but requires more complex and expensive hardware.

Stored Program Concept (SPC):

The foundational idea that a computer can store and execute instructions from memory, enabling programmable versatility.

Fetch-Execute Cycle:

The basic operation cycle of a CPU, where it fetches an instruction, decodes it, and executes it, sequentially.

Registers:

Small, fast storage locations in the CPU used to hold temporary data and instructions during processing.

Control Unit:

Directs the operation of the processor, managing the fetch-execute cycle and the flow of data within the CPU.

Address Bus:

Carries memory addresses from the processor to other components, determining where data should be retrieved or stored.

Data Bus:

Transmits actual data between the CPU, memory, and other peripherals.

Control Bus:

Carries control signals between the CPU and other components, managing and coordinating all activities within the computer.

Northbridge and Southbridge:

Components on a motherboard that connect the CPU to high-speed devices (Northbridge) and lower-speed peripherals (Southbridge).

Memory Mapped I/O:

Technique that allows device registers to be addressed as memory locations, simplifying device access by treating them as part of the memory.

Assembly Language

A low-level programming language that uses symbolic instructions, making it easier to understand and write than machine code.

Instruction Set Architectures (ISA):

Defines the set of instructions that a processor can execute, affecting how software is written and executed on hardware.

Stack Machine:

A computing model that uses a last-in, first-out (LIFO) stack to hold temporary data, making for simpler instruction sets but potentially slower execution.

Networking Stack

A set of networking protocols that work together to handle data communication over a network, often conceptualized as layers in a stack.

IPv4 vs. IPv6:

IPv4 is the fourth version of the Internet Protocol, using 32-bit addresses. IPv6 is its successor, using 128-bit addresses to provide a vastly larger number of unique IP addresses.

Multiplexing:

A method that combines multiple signals or data streams into one signal over a shared medium, improving efficiency.

Von Neumann vs. Harvard Architecture:

Von Neumann architecture uses the same memory and bus to store both data and instructions; Harvard architecture has separate memories and buses for data and instructions. Von Neumann architecture is MORE COMMON in general-purpose computers due to its simplicity and flexibility.

N-Way Mapping:

A compromise between direct-mapped and fully associative caches, where the cache is divided into sets and each set contains N lines. A block of memory can be placed in any line within a particular set, reducing conflict misses compared to direct mapping.

Direct Mapping:

Each block of memory is mapped to exactly one line in the cache. While simple and fast, it can lead to high conflict misses if many memory blocks map to the same cache line.

Fully Associative Mapping:

Any block of memory can be placed in any line of the cache, optimizing the use of cache memory but requiring more complex hardware to search the entire cache for a block.

Program Counter:

A register in the CPU that indicates where a computer is in its program sequence, typically pointing to the next instruction to be executed.

Cross-Platform Compatibility

Programs compiled for x86 architecture in Linux can often run in an x86 Windows environment, especially if they don't rely on OS-specific calls or if compatible libraries are available.

TCP Handshake:

A three-step process (SYN, SYN-ACK, ACK) used to establish a TCP connection between a client and a server.

IEEE 1394 (FireWire)

A standard for high-speed data transfer between electronic devices, often used in video and audio equipment.

Bandwidth

The number of bits transmitted per unit of time, also known as throughput.

Latency

The time it takes for a message to travel end-to-end across a network, composed of speed-of-light propagation delay, unit transmission time, and queuing delays.

Delay × Bandwidth Product

A measurement indicating how many bits "fit in the pipe"—the number of bits a sender must transmit before the first bit reaches the receiver (bits "in flight").

Encapsulation

The process where a lower-level protocol layer wraps a message from a higher layer by attaching a header (and possibly a trailer) to the payload.

Demultiplexing (Demux) Key

A field placed inside a protocol header that identifies which higher-level protocol or application the message belongs to.

Internet

A globally connected set of computer networks that all use a common suite of protocols; literally a network of networks.

Internet Layer

The TCP/IP layer that enables communication across networks by identifying hosts with addresses and routing data from network to network.

Link Layer

The layer closely tied to hardware (e.g., Wi-Fi, Ethernet, FDDI) that facilitates direct communication across a single local network.

MAC Address

A 6-byte Media Access Control address burned into each network interface card (NIC) that uniquely identifies a device on a local physical link.

Frame

The unit of data at the link layer, composed of a header, a data payload, and an error-detecting footer.

Subnet

A collection of computers on the same local network whose IP addresses share identical leading bits (network prefix), allowing direct communication at the link layer.

Network Prefix

The shared leading bits of an IP address that specify the subnet/network to which a device belongs.

Host Identifier

The trailing portion of an IP address that uniquely identifies an individual host within a given subnet.

Internet Stream Protocol

An experimental protocol assigned version number 5 that caused IPv5 to never be formally created as a public general-purpose IP release.

Segment

The protocol data unit transmitted at the transport layer by TCP.

Port Number

A transport-layer identifier that specifies the exact application process or service running on the host that should receive incoming data.

Ephemeral Port

A short-lived, temporary port assigned dynamically by the operating system to a client to facilitate communication with a server.

Endpoint

A networking abstraction defined by the combination of an IP address and a specific port number.

Socket

A concrete software instance of an endpoint.

IP Service Model

A delivery architecture based on connectionless, best-effort datagram delivery combined with a global host addressing scheme.

Datagram

A connectionless packet format that contains sufficient addressing information to be routed independently without advance path setup.

Time to Live (TTL)

An IPv4 header field operating as a hop count to restrict how far an IP packet can travel before being discarded.

Maximum Transmission Unit (MTU)

The maximum IP datagram size that can be encapsulated and carried inside a particular network frame type.

Fragmentation

The process of splitting an IP datagram into smaller chunks sharing an Ident field when traversing a link with a smaller MTU.

Flow Label

A 20-bit IPv6 header field used to hint to intermediate network devices that packets should follow identical network paths to preserve ordering.

Hop Limit

The IPv6 header field that directly replaces the IPv4 Time to Live (TTL) field to limit packet lifespan.

Network Address Translation (NAT)

A routing technique enabling private network devices to share a single public IP address by rewriting source and destination IP headers.