Computer Organization and Architecture: Complete Review

Comprehensive vocabulary flashcards covering Computer Organization and Architecture (11th Edition) Chapters 1, 11, 12, and 13.

Computer Architecture

Attributes of a computer system that are visible to the programmer and have a direct impact on the logical execution of a program, such as the instruction set, number of bits used to represent data types, I/O mechanisms, and memory addressing techniques.

Computer Organization

The operational units and their interconnections that realize architectural specifications, encompassing hardware details transparent to the programmer such as control signals, device interfaces, and memory technology.

Central Processing Unit (CPU)

The portion of a computer system that controls overall operations and executes data processing functions by fetching and executing instructions; comprises an Arithmetic and Logic Unit (ALU), a Control Unit, registers, and internal CPU interconnections.

Core

An individual processing unit situated on a processor chip that interprets and executes instructions, functioning equivalently to a CPU on a single-CPU computer system.

Processor

A physical piece of silicon containing one or more cores that interprets and executes machine instructions; referred to as a multicore processor when it houses multiple cores.

Cache Memory

Multiple layers of relatively small, high-speed memory situated between the processor and main memory used to buffer data that is likely to be accessed soon, reducing memory latency.

IAS Computer

A foundational first-generation computer based on the stored-program concept designed by John von Neumann, begun at the Princeton Institute for Advanced Studies and completed in $1952$.

Memory Buffer Register (MBR)

A register that contains a word to be stored into memory or sent to the I/O unit, or is used to receive a word retrieved from memory or the I/O unit.

Memory Address Register (MAR)

A register that specifies the address in memory of the word to be written from or read into the Memory Buffer Register (MBR).

Instruction Register (IR)

A register that contains the $8$-bit opcode of the machine instruction currently being executed by the processor.

Instruction Buffer Register (IBR)

A register employed to temporarily hold the right-hand instruction from an instruction word retrieved from memory in the IAS computer architecture.

Program Counter (PC)

A register that contains the address of the next instruction or instruction pair to be fetched from memory for execution.

Accumulator (AC) and Multiplier Quotient (MQ)

Registers employed to temporarily hold operands and results generated by Arithmetic and Logic Unit (ALU) operations.

Moore's Law

An observation made in $1965$ by Intel co-founder Gordon Moore stating that the number of transistors that could be put on a single chip doubled every year, later slowing to a doubling every $18$ months during the $1970\text{s}$.

Embedded System

A computing system combining electronics and dedicated software embedded within a larger product, often tightly coupled to its physical environment and constrained by real-time operating requirements.

Deeply Embedded System

A dedicated subset of embedded systems that utilizes a microcontroller with program logic permanently burned into ROM, operates without direct user interaction, and faces severe constraints on memory, size, time, and power consumption.

ARM Architecture

A family of RISC-based microprocessors and microcontrollers originally known as Acorn RISC Machine (now Advanced RISC Machine) designed by ARM Holdings, recognized for low power consumption and compact die size.

Arithmetic & Logic Unit (ALU)

The subsystem of the processor that executes all arithmetic calculations and Boolean logic operations on binary data.

Sign-Magnitude Representation

A signed integer format that assigns the most significant bit as a sign bit ($0$ for positive, $1$ for negative) and the remaining bits to express magnitude; it has the drawback of having two representations of zero ($+0$ and $-0$).

Twos Complement Representation

A signed binary integer convention where a negative number is formed by taking the Boolean complement of every bit of the corresponding positive integer and adding $1$; has a single representation for zero and an $n$-bit range of $-2^{n-1}$ through $2^{n-1} - 1$.

Sign Extension

The operation of increasing the bit length of a twos complement integer by moving the sign bit to the new leftmost position and filling all intervening positions with copies of the original sign bit ($0\text{s}$ for positive, $1\text{s}$ for negative).

Overflow Rule (Twos Complement)

The arithmetic rule stating that when two numbers with the same sign (both positive or both negative) are added, overflow occurs if and only if the resulting sum has the opposite sign.

Booth's Algorithm

A hardware multiplication algorithm designed to perform fast multiplication of signed binary numbers in twos complement notation by evaluating adjacent pairs of multiplier bits.

Floating-Point Normalization (IEEE 754)

A format convention where binary numbers are represented in the normalized form $\pm 1.b_1b_2b_3\dots \times 2^{\text{exp}}$, guaranteeing that the most significant bit to the left of the binary radix point is always a nonzero $1$.

Biased Exponent

A representation method for floating-point exponent fields where a fixed constant bias value equal to $2^{k-1} - 1$ is added to the true exponent, permitting nonnegative floating-point values to be compared like unsigned integers.

Significand Underflow

A floating-point processing condition where alignment shifts cause significant bits to flow off the right end of the significand, requiring rounding to preserve accuracy.

Interval Arithmetic

A precision-control computation technique that rounds lower bounds toward negative infinity ($-\infty$) and upper bounds toward positive infinity ($+\infty$) to produce an interval bounding the true result.

Truncation

A floating-point rounding method (also called 'round toward zero') in which all extra fractional bits are discarded, introducing an inherent bias toward zero in calculations.

Boolean Algebra

A mathematical discipline formulated by George Boole in $1854$ and applied to relay circuits by Claude Shannon, used to design, simplify, and analyze digital computer logic circuits using variables that take values of $0$ (FALSE) or $1$ (TRUE).

Combinational Circuit

An interconnected network of logic gates whose digital output at any given moment is solely a function of the current input signals, without possessing memory of previous input states.

Sequential Circuit

A digital circuit whose output at any time depends not only on the current inputs, but also on the past history of inputs, making use of combinational circuits combined with internal memory elements.

Karnaugh Map (K-Map)

A graphical tabular tool used in Boolean algebra to minimize Boolean expressions by mapping minterms into adjacent squares where common variable groupings can be identified visually.

Quine–McCluskey Method

A systematic tabular algorithm used to simplify complex Boolean algebraic expressions to their minimal sum-of-products form without relying on geometric K-map visualization.

Multiplexer (MUX)

A combinational logic circuit that routes one of multiple input data lines to a single common output line according to the binary value applied to its control select lines.

Decoder

A combinational circuit featuring $n$ input lines and up to $2^n$ output lines that activates exactly one unique output corresponding to the binary code presented at its inputs.

Read-Only Memory (ROM)

A combinational circuit storage unit that supports only read operations and produces a fixed binary output on data lines corresponding to the pattern present on its input address lines.

Flip-Flop

A bistable sequential electronic device that serves as a $1$-bit storage element by existing in one of two stable states and producing two outputs ($Q$ and $\overline{Q}$) that are always logical complements of each other.

S–R Latch

The simplest bistable sequential circuit constructed from cross-coupled NOR or NAND gates having Set ($S$) and Reset ($R$) inputs, in which the input condition $S=1, R=1$ produces an invalid/undefined output state.

J-K Flip-Flop

A clocked flip-flop design that eliminates the undefined state of an S-R flip-flop by causing the output state to toggle ($Q_{n+1} = \overline{Q}_n$) when both the $J$ and $K$ inputs are set to $1$.

D Flip-Flop

A clocked sequential circuit device containing a single data input ($D$) whose logic level is transferred directly to the output ($Q$) upon the arrival of an active clock transition.

Ripple Counter

An asynchronous sequential counting circuit consisting of flip-flops connected in series where the output of each flip-flop triggers the clock input of the succeeding flip-flop.

Synchronous Counter

A sequential counting circuit where all internal flip-flops share a common clock input and transition states simultaneously, avoiding cascading propagation delays.

Programmable Logic Array (PLA)

A programmable logic device consisting of two levels of logic featuring both a programmable AND array and a programmable OR array.

Field-Programmable Gate Array (FPGA)

A high-density programmable logic device characterized by an array of configurable logic blocks, narrow logic resources, programmable interconnects, and a higher ratio of flip-flops to logic gates compared to CPLDs.

Machine Instruction

An individual instruction formulated as a sequence of binary bits that directs processor operations, partitioned into an operation code (opcode) and one or more operand references.

Instruction Set

The complete collection of distinct machine instructions that a specific processor is capable of decoding and executing.

Immediate Operand

An operand addressing format where the value of the operand is contained directly within a designated field of the machine instruction being executed.

Memory-Mapped I/O

An I/O interfacing scheme where I/O module registers and device ports share the common memory address space and are addressed using standard memory reference instructions.

Skip Instruction

A transfer-of-control instruction containing an implied address that causes the processor to skip the subsequent instruction by advancing the program counter past it (such as the increment-and-skip-if-zero, or ISZ, instruction).

Big Endian

A byte-ordering format where the most significant byte of a multibyte scalar value is placed at the lowest numerical byte memory address ('the big end').

Little Endian

A byte-ordering format where the least significant byte of a multibyte scalar value is placed at the lowest numerical byte memory address ('the little end').

Packed Decimal (BCD)

A numeric data representation format in which each decimal digit is encoded into a $4$-bit binary value, allowing two decimal digits to be packed into each $8$-bit byte.

Single Instruction, Multiple Data (SIMD)

An architectural instruction execution paradigm (implemented in extensions such as Intel MMX and SSE) where a single instruction operates simultaneously across parallel vectors of packed data elements.