Computer Organization and Architecture

Comprehensive practice flashcards defining foundational vocabulary, concepts, formulas, and architectures across computer organization, arithmetic design, processor datapaths, pipelining, and parallelism.

Radix (Base)

The total number of unique digits used to represent numbers in a positional number system, including the digit $0$.

Diminished Radix Complement

A complement for an $n$-digit base-$r$ number $N$ defined as $(r^n - 1) - N$, represented as the $(r-1)\text{'s}$ complement (e.g., $1\text{'s}$ complement in binary or $9\text{'s}$ complement in decimal).

Radix Complement

A complement for an $n$-digit base-$r$ number $N$ defined as $r^n - N$, equivalent to adding $1$ to the diminished radix complement ($(r-1)\text{'s}$ complement $+ 1$).

Gray Code

An unweighted binary code in which only a single bit changes when transitioning from one numerical value to the next, commonly utilized in analog-to-digital converters.

ASCII (American Standard Code for Information Interchange)

A standard 7-bit binary code representing $128$ alphanumeric characters ($2^7$), consisting of $26$ uppercase letters, $26$ lowercase letters, $10$ numerals ($0$ to $9$), $32$ printable characters, and $34$ control characters.

Universal Gate

A digital logic gate (such as a NAND or NOR gate) capable of implementing any Boolean function and realizing AND, OR, and NOT operations without requiring other gate types.

Instruction Set Architecture (ISA)

The programmer-visible machine interface that defines aspects of computer design such as the instruction set, registers, memory organization, and exception handling.

Computer Organization

The high-level structural design and operational interconnects of a computer system, including the memory system, bus structure, and internal CPU design.

Big-Endian

A byte-ordering scheme where the most significant byte of a word is stored at the lowest memory address in the sequence.

Little-Endian

A byte-ordering scheme where the least significant byte of a word is stored at the lowest memory address in the sequence.

Program Counter (PC)

A processor register that holds the memory address of the next instruction to be fetched and executed.

Instruction Register (IR)

A processor register that holds the instruction currently being executed and decoded.

Memory Address Register (MAR)

A processor register connected to the address lines that holds the specific memory address to be accessed for reading or writing.

Memory Data Register (MDR)

A two-input, two-output processor register connected to data lines that holds data read from or written to an addressed memory location.

Straight Line Sequencing

The process of executing instructions in a strictly sequential order where the Program Counter is incremented by a fixed offset after each instruction without loading branch addresses.

Register Indirect Addressing Mode

An addressing mode in which the instruction specifies a processor register containing the effective memory address of the operand, requiring one memory reference to retrieve the data.

Indexed Addressing Mode

An addressing mode in which the effective address of the operand is computed by adding the contents of an index register to the address part specified in the instruction.

Interrupt Service Routine (ISR)

A dedicated software routine executed by the processor to service an asynchronous hardware request (interrupt) received from an I/O device.

Half Adder

A combinational arithmetic circuit with two single-bit binary inputs ($A$ and $B$) and two outputs: Sum ($S = A \bar{B} + \bar{A} B = A \bigoplus B$) and Carry ($C = A B$).

Full Adder

A combinational circuit that adds two one-bit operands ($A$ and $B$) and a carry-in ($C_{in}$) to produce a Sum ($S = A \bigoplus B \bigoplus C_{in}$) and a Carry-out ($C_{out} = (A \bigoplus B) C_{in} + A B$).

Carry Look-Ahead Adder (CLA)

A fast adder circuit that eliminates the ripple delay of cascaded stages by calculating carry-in signals simultaneously in advance using generate ($G_i = A_i B_i$) and propagate ($P_i = A_i \bigoplus B_i$) terms.

Booth's Algorithm

A signed binary multiplication algorithm that treats positive and negative two's-complement numbers uniformly and accelerates processing by reducing additions through multiplier recoding into $0$, $+1$, and $-1$.

Bit-Pair Recoding

A multiplication technique derived from Booth's algorithm that evaluates overlapping triplets of multiplier bits to halve the maximum number of summands required for an $n$-bit operand to $\frac{n}{2}$.

Carry-Save Adder (CSA)

A digital multi-operand adder (3-2 adder) that sums three binary vectors simultaneously to generate separate sum and carry vectors without carry propagation between adjacent bit stages.

Restoring Division

A binary division method where the divisor is subtracted from the shifted partial remainder; if the result is negative ($A < 0$), the quotient bit is set to $0$ and the divisor is added back to restore the previous value of register $A$.

Non-Restoring Division

A division algorithm that eliminates the restorative addition step by adding the divisor in the subsequent cycle if the partial remainder is negative ($2A + M$), or subtracting it if positive ($2A - M$).

IEEE 754 Single Precision

A 32-bit floating-point representation standard configured with a 1-bit sign, an 8-bit exponent biased by $127$, and a 23-bit normalized mantissa.

Datapath

The collective hardware structure within a processor—composed of general-purpose registers, the ALU, multiplexers, and interconnecting internal buses—that carries and manipulates data.

Hardwired Control Unit

A fast, fixed-logic control unit implemented as a finite state machine that generates control signals directly using combinational circuits, step counters, decoders, and condition flags.

Microprogrammed Control Unit

A flexible control unit design where control signals are generated by sequentially fetching and executing binary microinstructions (control words) stored in a control store memory.

Pipeline Hazard

Any condition—categorized as structural, data, or control—that prevents the next instruction in an instruction stream from executing during its designated clock cycle, resulting in a stall.

Structural Hazard

A pipeline stall occurring due to a hardware resource conflict when two or more instructions require access to the same functional unit or memory port simultaneously.

Data Hazard

A pipeline hazard that occurs when an instruction depends on the result of an earlier instruction that has not yet completed execution and writeback.

Operand Forwarding (Bypassing)

A technique to mitigate data hazard stalls by routing execution results directly from pipeline register outputs back to ALU inputs without waiting for register file writeback.

Delayed Branch

A branch hazard mitigation technique where the instruction(s) immediately following a branch instruction (in the branch delay slot) are always fetched and executed regardless of whether the branch is taken.

Instruction-Level Parallelism (ILP)

A measure of how many operations within an instruction stream can be executed concurrently without violating data or control dependencies.

Data-Level Parallelism (DLP)

A parallel processing model where identical instructions are executed concurrently across multiple processing elements on separate segments of distributed data.

SIMD (Single Instruction, Multiple Data)

A class of parallel architecture in Flynn's taxonomy where a single control unit broadcasts one instruction to multiple processing units that execute it simultaneously on different data elements.

Load-Store Architecture

A processor architecture feature (used in RISC and ARM) where data processing operations are performed exclusively within registers, and memory is accessed only via explicit load and store instructions.

Barrel Shifter

A functional unit in the ARM datapath capable of shifting or rotating a 32-bit register operand by an arbitrary number of bits within a single clock cycle prior to ALU execution.

Thumb Instruction Set

A 16-bit compressed instruction set variant of the ARM architecture that offers improved code density and reduces external memory bus power consumption.

Current Program Status Register (CPSR)

A 32-bit ARM processor register holding condition code flags ($N$, $Z$, $C$, $V$), interrupt disable bits ($I$, $F$), execution state bits ($T$, $J$), and processor mode selection bits.

Memory-Mapped I/O

An input/output interfacing scheme in which I/O port registers share the standard memory address space and are accessed using regular memory manipulation instructions (such as MOVE, LOAD, and STORE).