COMARC - 555 Timer IC

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114 Terms

1
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The integrated circuit designed by Hans Camenzind in 1972

one of the most popular and versatile ICs ever produced

2
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The commercial-grade version of the 555 timer with an operating temperature range of 0°C to 70°C

NE-555

3
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The military-grade version of the 555 timer with an operating temperature range of -55°C to 125°C

SE-555

4
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The input pin that sets the output HIGH when its voltage drops below 1/3 Vcc

Trigger (Pin 2)

5
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The input pin that resets the output LOW when its voltage rises above 2/3 Vcc

Threshold (Pin 6)

6
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The output pin connected to an internal NPN transistor that drains the external timing capacitor

Discharge (Pin 7)

7
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The active-low input pin that forces the output LOW regardless of other inputs and should be tied to Vcc if unused

Reset (Pin 4)

8
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The pin that allows external adjustment of the internal reference voltages and is often bypassed with a capacitor

Control Voltage (Pin 5)

9
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The internal memory element that stores the current output state

set by the Trigger comparator and reset by the Threshold comparator

10
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The internal circuit consisting of three 5 kΩ resistors connected in series between Vcc and Ground that creates reference voltages of 1/3 Vcc and 2/3 Vcc

Voltage divider

11
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The internal circuit that drives the Output pin (Pin 3) high or low based on the flip-flop's state

Output Driver

12
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The internal component that compares the Trigger pin voltage against the 1/3 Vcc reference and feeds the Set input of the flip-flop

Comparator 1 (Trigger comparator)

13
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The internal component that compares the Threshold pin voltage against the 2/3 Vcc reference and feeds the Reset input of the flip-flop

Comparator 2 (Threshold comparator)

14
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The 555 configuration with no stable state where the output continuously oscillates producing a square wave without external triggering

Astable Multivibrator

15
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The 555 configuration with one stable state (low) that produces a single output pulse per external trigger

Monostable Multivibrator

16
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The 555 configuration with two stable states (high and low) that behaves like a simple flip-flop or on-off switch

Bi-stable Multivibrator

17
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In astable mode

the resistor that connects +Vcc to the Discharge pin (Pin 7) with a typical value of 1 kΩ

18
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In astable mode

the resistor that connects the Discharge pin (Pin 7) to the joined Threshold/Trigger node with a typical value of 100 kΩ

19
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The timing capacitor in astable mode with a typical value of 1 μF (electrolytic) that connects the Threshold/Trigger node to Ground

C1

20
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The pin that is tied directly to +Vcc in astable mode so the timer is never held in reset

Reset (Pin 4)

21
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The capacitor placed on Pin 5 (Control Voltage) in astable mode to filter the output signal

0.01 μF capacitor

22
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The capacitor placed from Vcc to Ground in astable mode to filter supply voltage "shoot up" (noise)

0.1 μF capacitor

23
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In monostable mode

the timing resistor with a typical value of 1 MΩ that connects +Vcc to the joined Discharge/Threshold node

24
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In monostable mode

the timing capacitor with a typical value of 0.1 μF on Pin 6 that connects the Discharge/Threshold node to Ground

25
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In monostable mode

the component that pulls the Trigger pin (Pin 2) up to +Vcc so it idles HIGH

26
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In monostable mode

the input device used to momentarily pull the Trigger pin LOW (below 1/3 Vcc) to start the pulse

27
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In monostable mode

the additional component placed on the trigger switch to prevent false triggering from contact bounce

28
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In bi-stable mode

the component that pulls the Trigger pin (Pin 2) up to +5V so it idles HIGH

29
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In bi-stable mode

the component that pulls the Reset pin (Pin 4) up to +5V so it idles HIGH (not held in reset)

30
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In bi-stable mode

the switch that momentarily connects Pin 2 (Trigger) to ground to set the output HIGH

31
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In bi-stable mode

the switch that momentarily connects Pin 4 (Reset) to ground to reset the output LOW

32
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The pin that is tied directly to Ground in bi-stable mode (permanently disabled so the timer never resets itself)

Threshold (Pin 6)

33
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The pin that is left unconnected/unused in bi-stable mode because there is no external timing capacitor

Discharge (Pin 7)

34
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In bi-stable mode

the LED and resistor connected from Output (Pin 3) to Ground to visually indicate the output state

35
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The package type of the 555 timer IC with 8 pins (four on each side)

DIP-8 package

36
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The reference voltage at which the Trigger comparator trips to set the output HIGH

1/3 Vcc

37
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The reference voltage at which the Threshold comparator trips to reset the output LOW

2/3 Vcc

38
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The origin of the name "555 timer" derived from the three internal resistors that form the voltage divider

Three 5 kΩ resistors

39
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The process in astable mode where the capacitor charges through both R1 and R2 while the Output is HIGH

Charging phase

40
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The process in astable mode where the capacitor discharges through R2 only through Pin 7 while the Output is LOW

Discharging phase

41
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The proportion of time the astable output stays HIGH versus LOW during one oscillation cycle

Duty Cycle

42
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A 555 configuration used for generating clock pulses

PWM signals

43
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A 555 configuration used for pulse generation

timers

44
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A 555 configuration used for flip-flops

memory circuits

45
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The condition in the resting state of the monostable circuit where the Trigger pin is held HIGH by its pull-up resistor and the Output stays LOW

Idle state

46
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The condition where Threshold and Trigger pins are tied together at the same node as the timing capacitor in astable mode

Self-triggering loop

47
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The critical wiring difference in bi-stable mode where grounding the Threshold pin permanently disables the Threshold comparator

Threshold grounded

48
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The number of stable states in Astable mode

0

49
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The number of stable states in Monostable mode

1

50
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The number of stable states in Bi-stable mode

2

51
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The output behavior of Astable mode where the output continuously oscillates

Continuously oscillates

52
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The output behavior of Monostable mode where the output produces one pulse per trigger and then returns low

One pulse per trigger

53
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The output behavior of Bi-stable mode where the output toggles and holds until switched again

Toggles and holds until switched again

54
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The Threshold pin connection in Astable mode where it is tied to the timing capacitor node with Trigger

Tied to timing capacitor node (with Trigger)

55
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The Threshold pin connection in Monostable mode where it is tied to the timing capacitor node with Discharge

Tied to timing capacitor node (with Discharge)

56
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The Threshold pin connection in Bi-stable mode where it is tied directly to Ground

Tied directly to Ground (disabled)

57
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The typical use for Astable mode

Clock pulses

58
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The typical use for Monostable mode

Delay circuits

59
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The typical use for Bi-stable mode

Flip-flops

60
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The memory tip for counting stable states: A-stable = 0

Mono-stable = 1

61
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In astable mode

the capacitor charges through both R1 and R2

62
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The memory tip that describes astable charging and discharging

"charge long

63
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The component that provides a path to ground to discharge the external timing capacitor when turned on

NPN Discharge transistor

64
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The key difference between astable and monostable regarding Trigger and Threshold pins

In astable they are tied together

65
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in monostable they are separate

66
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The reason the astable output is not a perfectly symmetric 50/50 square wave

Capacitor charges through R1+R2 but discharges through R2 only

67
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The NE-555 variant has a narrower operating temperature range than the SE-555 variant

False

68
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The NE-555 and SE-555 variants have identical internal operation

True

69
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The 555 timer gets its name from the five 5Ω resistors inside the IC

False

70
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The Trigger pin (Pin 2) sets the output HIGH when its voltage drops below 1/3 Vcc

True

71
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The Threshold pin (Pin 6) sets the output HIGH when its voltage rises above 2/3 Vcc

False

72
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The Reset pin (Pin 4) is active-high and should be grounded if unused

False

73
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The Control Voltage pin (Pin 5) allows external adjustment of the internal reference voltages

True

74
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The 555 timer's internal voltage divider uses four 5kΩ resistors

False

75
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The internal SR Flip-Flop is set by the Threshold comparator and reset by the Trigger comparator

False

76
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The Discharge pin (Pin 7) is connected to an internal NPN transistor that provides a path to ground

True

77
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The astable multivibrator has no stable state and continuously oscillates

True

78
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The monostable multivibrator has two stable states and toggles between them

False

79
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The bi-stable multivibrator behaves like a simple flip-flop or on-off switch

True

80
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In astable mode

the Reset pin (Pin 4) is tied to Ground

81
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In astable mode

a 0.01 μF capacitor is placed on Pin 5 (Control Voltage) to filter the output signal

82
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In astable mode

a 0.1 μF capacitor is placed from Vcc to Ground to filter supply voltage "shoot up"

83
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In monostable mode

the timing capacitor charges through R1 and discharges through R2

84
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In monostable mode

the Trigger pin is held LOW by its pull-down resistor in the resting state

85
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In monostable mode

pressing the push button pulls the Trigger pin below 1/3 Vcc to start the pulse

86
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In bi-stable mode

the Threshold pin is tied directly to Ground

87
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In bi-stable mode

the Discharge pin (Pin 7) is used as the timing capacitor connection

88
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In bi-stable mode

pressing the Set switch (Trigger) makes the Output go LOW

89
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In bi-stable mode

pressing the Reset switch (Pin 4) forces the Output LOW

90
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The astable mode is used for delay circuits and pulse generation

False

91
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The monostable mode is used for flip-flops and memory circuits

False

92
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The bi-stable mode is used for on-off switches and memory circuits

True

93
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All three 555 modes use the same internal comparators and flip-flop — only external pin wiring changes

True

94
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In astable mode

the capacitor charges through R2 only and discharges through R1 + R2

95
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The bi-stable mode operates as a push-button light switch: one button turns the LED ON (Set/Trigger)

the other turns it OFF (Reset)

96
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In monostable mode

the Trigger and Threshold pins are tied together at the same timing node

97
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In astable mode

the output stays HIGH while the capacitor is charging and stays LOW while the capacitor is discharging

98
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The Discharge transistor turns ON when the internal flip-flop is SET (Output HIGH)

False

99
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The Control Voltage pin (Pin 5) is often bypassed with a capacitor to filter out noise and stabilize the reference voltages

True

100
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The 555 timer can only operate in astable mode