1.1- Structure + Function of the processor

def clock speed

number of clock cycles per second

def number of cores

independent processing units that can FDE at the same time

def cache size

amount of high speed memory inside the CPU

stores frequently used instructions

give examples of registers

PC, ACC, MAR, MDR, CIR

def CIR

Holds the current instruction fetched from memory before it is decoded + executed (before being split into opcode + operand)

Def data bus

transfers data + instructions between CPU components

def address bus

transfers the memory address of where data or instructions are to be R or W

def control bus

transfers control signals used to manage the operation of the computer system

def FDE

the continuous process carried out by the CPU to execute every instruction in a program

explain the decode stage:

instruction is copied from MDR to CIR

CIR splits instruction into opcode = operand

CU decodes the instruction

explain execute stage

where the instruction is carried out

ALU performs calculations if needed

data may be read from or written to memory

the result is stored in memory

def pipelining

process of carrying out multiple instructions concurrently (at same time)

one instruction can be fetched while the previous one is being decoded and the one before that is being executed

How does pipelining improve processor performance?

increases instruction throughput (more instructions completed per unit time)

CPU components are used continuously, reducing idle time

multiple stages operate simultaneously (fetch, decode + execute cycles overlap)

all parts of processor can be used at any instance

def Von Neumann architchture

A system where data + instructions are stored in the same memory + use shared buses

def Harvard architechture

a system with seperate memory and buses for data and instructions, allowing independent access

def CU

coordinates and controls CPU operations, managing the FDE cycle + sending control signals

def ALU

carries out arithmetic + logic operations in computer such as: addition + comparison

def RAM

main memory that temporarily stores data + instructions currently being used, allowing fast access by the CPU

DIS of Von Neumann

Instructions + data compete for the same bus

CPU may have to wait before transferring data

ADV of harvard

CPU can fetch data + instructions simultaneously

less waiting

faster execution

better performance

Why is harvard faster

seperate memories - instruction + data access happen together

seperate buses - no competition between data + instructions

supports pipelining - fetch, decode + execute overlap