CMOS EXAM 1

content for exam 1, based on practice exam 1 questions (multiple choice/fill in the blank) and some questions generated by AI.

PMOS transistor is a good conductor of…

1s

PMOS transistor is a bad conductor of…

0s

CMOS stands for…

Complementary Metal Oxide Semiconductor

The majority carriers in n-type Si are…

Electrons

The minority carriers in n-type Si are

Holes

What is threshold voltage of a MOSFET?

Threshold voltage Vt is the minimum gate-to-source voltage above/below which the NMOS/PMOS begins to conduct

Why do we usually draw the length of a CMOS transistor equal to the minimum

allowable length in a technology?

Ids is inversely proportional to L. Usually we design for fast gates. Hence, we keep L to minimum allowable lengths.

_______ is a poor conductor of electricity.

Pure Silicon

n a static CMOS circuit, ______ section is responsible for pulling the output to

logic “1”.

PMOS

In the saturation mode of a MOSFET, the carrier conduction is due to

__________ _______mechanism.

Carrier drift

In a static CMOS circuit, we usually limit the number of transistors in series to 3

or 4, because________________

body effect

The mobility of electrons is____________ that of holes

Greater than

Gate tunneling current arises due to:

Thin Oxide

ds is directly proportional to:___________________

Transistor width

A transmission gate is a good conductor of…

both 1’s and 0’s

In linear mode of an ideal nMOS transistor:___________________

Ids is proportional to Vgs.

Transmission gate based 2-input multiplexer needs___________ transistors

6

Maximum power consumption is checked at the following design corner

NMOS=Fast, PMOS=Fast, Temperature=Low

The gate capacitance of a CMOS transistor is:

Depends on the mode of operation

nMOS is a good conductor of...

0s

nMOS is a poor conductor of...

1s

nMOS turns ON when...

V_GS > V_TN

pMOS turns ON when...

V_SG > |V_TP|

The majority carriers in p-type silicon are...

Holes

The minority carriers in p-type silicon are...

Electrons

n-type silicon is doped with...

Donor impurities (Group V)

p-type silicon is doped with...

Acceptor impurities (Group III)

What is the body effect?

A change in threshold voltage caused by source-to-body voltage

Why is pMOS typically wider than nMOS?

To compensate for lower hole mobility

What are the three operating regions of a MOSFET?

Cutoff, Linear, Saturation

nMOS cutoff condition?

V_GS < V_T

nMOS linear condition?

V_GS > V_T and V_DS < V_GS - V_T

nMOS saturation condition?

V_GS > V_T and V_DS >= V_GS - V_T

What is I_DS in ideal cutoff?

0 A

What happens to the inversion channel in saturation?

It pinches off near the drain

What is overdrive voltage?

V_OV = V_GS - V_T

What is the nMOS saturation current equation?

Ids = (1/2) * μn * Cox * (W/L) * (Vgs - Vt)²

What is the nMOS linear current equation?

Ids = μn * Cox * (W/L) * [(Vgs - Vt) * Vds - (Vds²/2)]

In ideal saturation, I_DS is independent of...

V_DS

What causes current to flow through the MOSFET channel?

Carrier drift due to an electric field

What is the pull-up network made of?

pMOS transistors

What is the pull-down network made of?

nMOS transistors

Pull-down network connects output to...

Ground (GND)

Pull-up network connects output to...

V_DD

How many transistors in a CMOS inverter?

2

How many transistors in a 2-input NAND?

4

How many transistors in a 2-input NOR?

4

In a 2-input NAND gate, the nMOS transistors are...

Series

In a 2-input NOR gate, the nMOS transistors are...

Parallel

In a 2-input NAND gate, the pMOS transistors are...

Parallel

In a 2-input NOR gate, the pMOS transistors are...

Series

In static complementary CMOS, the PUN and PDN are...

Dual networks (series ↔ parallel)

What does an AOI gate mean?

AND-OR-Invert

What does an OAI gate mean?

OR-AND-Invert

How many transistors does a CMOS AOI21 gate require, excluding input inverters?

6

How many transistors in one transmission gate?

2 (one nMOS, one pMOS)

What control signals operate a transmission gate?

Complementary signals

How many transistors in a transmission-gate 2:1 MUX including select inverter?

6

What is the main difference between a latch and a flip-flop?

Latch: level-sensitive; flip-flop: edge-triggered

A positive-level D latch is transparent when...

CLK = 1

A positive-edge D flip-flop updates on...

Rising clock edge

A conventional master-slave D flip-flop uses...

Two latches

What does a stick diagram represent?

Simplified layout showing layer connections and topology

What forms a MOSFET where it crosses active diffusion?

Polysilicon gate

What is the purpose of CMOS design rules?

Ensure manufacturable layouts

What is a minimum spacing rule?

Minimum allowed separation between specified features

What is a minimum width rule?

Minimum allowable feature width

Where are pMOS transistors typically placed in standard CMOS layout?

n-well

Where are nMOS transistors typically placed in an n-well CMOS process?

p-type substrate

What do contacts and vias provide?

Electrical connections between specified layers

What is channel-length modulation?

Effective channel length decreases as V_DS increases in saturation

What is subthreshold leakage?

Small drain current even when V_GS < V_T

What is velocity saturation?

Carrier velocity stops increasing proportionally with electric field

What causes gate leakage?

Electron tunneling through thin gate oxide

What is DIBL?

Drain-Induced Barrier Lowering

What is the effect of DIBL?

High drain voltage reduces effective threshold voltage

What is the main source of CMOS dynamic power?

Charging and discharging capacitances

What causes short-circuit power in CMOS?

Temporary simultaneous conduction of pMOS and nMOS during switching