digital and sequentila flash cards

Polarisation in liquid crystal displays (LCDs)

Application of a polarising filter as a grid that allows light waves of a single orientation to pass while blocking other planes. In an LCD display, two layers of polarised glass can be aligned or misaligned electrically to pass or block light waves. Light passing through Grid A becomes vertically polarised, while Grid D blocks it because its gridlines are rotated $90^\circ$ relative to Grid A.

Creation of a picture on an LCD screen

Each pixel in the matrix is controlled by its own thin-film transistor (TFT) that turns the energising voltage on or off. By energising different pixels using the transistor array, pixels become visible, and the combined visible pixels form a coherent number, letter, or image.

Common anode vs. common cathode LED seven-segment display

In a Common Anode connection, the anodes of all eight LEDs are internally connected together to a common positive voltage rail $+V$. In a Common Cathode connection, the cathodes of all eight LEDs are internally connected together to a common $0\,\text{V}$ ground rail.

Sinking output vs. sourcing output

A sinking output has the transistor collector connected to the LED's cathode (using an NPN transistor). A sourcing output has the transistor emitter connected to the LED's anode (using a PNP transistor).

Main purpose of a seven-segment display driver

To provide the necessary current to activate or illuminate the seven-segment display and convert a 4-bit binary code into a 7-segment binary code so the display can show a decimal number to the user.

Function of driver transistors in BCD-to-seven-segment display decoders

Driver transistors are used to feed each LED display segment separately to ensure that all bars and segments of a displayed number are illuminated to the same brightness level.

Function of an encoder

Accepts input data in decimal form (such as push-buttons 0 to 9) and converts this information into a corresponding binary code or form.

Function of a decoder

Converts a binary code at its inputs into a recognisable decimal form or individual output format, such as driving a display or selecting a specific output line.

Differences between a full adder and a half adder

(a) Inputs: A full adder has three inputs $A$, $B$, and Carry-In $C_i$, whereas a half adder has two inputs $A$ and $B$. (b) Logic Gates: A full adder consists of two XOR gates, two AND gates, and one OR gate, whereas a half adder consists of only one XOR gate and one AND gate (containing no OR gate).

RS flip-flop as a memory cell

The RS flip-flop is a bistable element that can maintain or latch its output state $Q$ indefinitely even after the triggering input signals are removed, storing 1 bit of binary data until a new set or reset signal is applied.

Pulse-triggered vs. edge-triggered flip-flops

Pulse-triggered: Allows the circuit to change state at any time during the entire HIGH level duration of the clock pulse. Edge-triggered: The flip-flop changes state strictly at the transition boundary, either on the rising edge or falling edge of the clock waveform.

Positive vs. negative edge triggering

Positive Edge Triggering: The flip-flop is triggered to change state on the LOW-to-HIGH ($0 \rightarrow 1$) transition of the clock pulse. Negative Edge Triggering: The flip-flop is triggered to change state on the HIGH-to-LOW ($1 \rightarrow 0$) transition of the clock pulse.

Propagation delay in asynchronous counters

Propagation delay is the time lag introduced as a signal ripples through sequential flip-flop stages. In asynchronous counters, only the first flip-flop is clocked directly, causing a cumulative delay through successive stages. It can be eliminated by using synchronous counting, where all flip-flops are fed simultaneously by a common clock pulse.

Synchronous counter vs. asynchronous counter

Asynchronous Counter: Flip-flops are not triggered at the same time; only the first stage receives the main clock pulse, while preceding outputs trigger subsequent stages. Synchronous Counter: All flip-flops are triggered simultaneously by the exact same clock pulse.

Definition of a digital counter

A counter is a sequential logic circuit that counts through a set sequence of numbers when activated by clock pulses, and once the final count is reached, it returns to its original starting state.

Function of the AND gate in a synchronous binary counter

Decodes the outputs of preceding stages $Q<em>0$ and $Q</em>1$ to ensure that the next flip-flop enters toggle mode only when all preceding bits are HIGH (1), preventing premature toggling and maintaining the correct binary sequence.

Why down counters operate faster than up/down counters

A down counter has fewer logic gates than an up/down counter, which reduces internal gate propagation delays and allows it to operate at a higher speed.

Disadvantage of an up/down counter

Up/down counters are slower than standard up or down counters due to the extra steering logic gate delays between flip-flop stages.

Operation of up/down counter steering logic

When the Up/Down control line is HIGH (1), it enables one set of AND gates connected to the $Q$ outputs, steering $Q$ to the next flip-flop clock input for Up counting. When the control line is LOW (0), the inverter enables the second set of AND gates connected to $\bar{Q}$ outputs, steering $\bar{Q}$ signals to perform Down counting.

Sequential operation of a synchronous self-stopping up-counter

Initially, all flip-flops are cleared to $000<em>2$. All flip-flops are clocked simultaneously by the main clock signal. On each pulse, $FF</em>0$ toggles (LSB) and $FF<em>1$ toggles when $Q</em>0 = 1$. The AND gate decodes when both $Q<em>0 = 1$ and $Q</em>1 = 1$, enabling $FF<em>2$ (MSB) to toggle. When the counter reaches its designated target stop count (e.g., $101</em>2$ / decimal 5), feedback logic disables further clock pulses from toggling the flip-flops, freezing the count at that state.

Counter Classifications (Full-Sequence, Truncated, Decade, Frequency Divider)

Full-Sequence Counter: Counts through its complete natural binary capacity (0 to $2^n - 1$) before resetting. Truncated Counter: Modified using feedback gates to reset or stop its count before reaching its maximum natural count capacity. Decade Counter: A binary counter designed to count from $0000<em>2$ (decimal 0) to $1001</em>2$ (decimal 9) and automatically reset to $0000_2$ on the tenth pulse. Frequency Divider: A counter that divides the input clock frequency of each preceding stage, creating a chain of successive half-frequency output signals.

Definition of a digital register

A register is a sequential circuit that shifts binary data into the register, stores the data as a word, and then moves or shifts the bits of the stored word out when required by clock pulses.

Serial-In: Serial-Out (SISO) register operation

Data enters the register one bit at a time on each clock pulse and leaves the register one bit at a time in a serial manner from the final flip-flop stage.

Parallel-In: Serial-Out (PISO) register operation

All 4 bits of binary data are loaded into the register flip-flops simultaneously in parallel. Once stored, clock pulses sequentially shift the data out one bit at a time from the serial output line.

Serial-In: Parallel-Out (SIPO) register operation

Data is clocked into the register one bit at a time, shifting one position to the right with each clock pulse until the complete 4-bit word is stored. The full stored word then appears on all parallel output lines simultaneously.